97 lines
2.4 KiB
Systemverilog
97 lines
2.4 KiB
Systemverilog
`timescale 1ns / 1ps
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`default_nettype none
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module top_level (
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input wire clk_100mhz,
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input wire uart_txd_in,
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output logic uart_rxd_out,
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output logic [3:0] vga_r, vga_g, vga_b,
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output logic vga_hs, vga_vs);
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// Clock generation
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logic clk_65mhz;
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clk_gen gen(
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.clk_100mhz(clk_100mhz),
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.clk_50mhz(),
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.clk_65mhz(clk_65mhz));
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// VGA signals
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logic [10:0] hcount;
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logic [9:0] vcount;
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logic hsync, vsync, blank;
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vga vga_gen(
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.pixel_clk_in(clk_65mhz),
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.hcount_out(hcount),
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.vcount_out(vcount),
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.hsync_out(hsync),
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.vsync_out(vsync),
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.blank_out(blank));
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// VGA Pipelining
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reg[1:0][10:0] hcount_pipe;
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reg[1:0][10:0] vcount_pipe;
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reg[1:0] hsync_pipe;
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reg[1:0] vsync_pipe;
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reg[1:0] blank_pipe;
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always_ff @(posedge clk_65mhz)begin
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hcount_pipe[0] <= hcount;
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vcount_pipe[0] <= vcount;
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hsync_pipe[0] <= hsync;
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vsync_pipe[0] <= vsync;
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blank_pipe[0] <= blank;
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for (int i=1; i<2; i = i+1)begin
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hcount_pipe[i] <= hcount_pipe[i-1];
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vcount_pipe[i] <= vcount_pipe[i-1];
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hsync_pipe[i] <= hsync_pipe[i-1];
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vsync_pipe[i] <= vsync_pipe[i-1];
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blank_pipe[i] <= blank_pipe[i-1];
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end
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end
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localparam WIDTH = 128;
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localparam HEIGHT = 128;
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localparam X = 0;
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localparam Y = 0;
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// calculate rom address
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logic [$clog2(WIDTH*HEIGHT)-1:0] image_addr;
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assign image_addr = (hcount - X) + ((vcount - Y) * WIDTH);
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logic in_sprite;
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assign in_sprite = ((hcount_pipe[1] >= X && hcount_pipe[1] < (X + WIDTH)) &&
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(vcount_pipe[1] >= Y && vcount_pipe[1] < (Y + HEIGHT)));
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manta manta_inst (
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.clk(clk_65mhz),
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.rx(uart_txd_in),
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.tx(uart_rxd_out),
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.image_mem_clk(clk_65mhz),
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.image_mem_addr(image_addr),
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.image_mem_din(),
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.image_mem_dout(sprite_color),
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.image_mem_we(1'b0));
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logic [11:0] sprite_color;
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logic [11:0] color;
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assign color = in_sprite ? sprite_color : 12'h0;
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// the following lines are required for the Nexys4 VGA circuit - do not change
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assign vga_r = ~blank_pipe[1] ? color[11:8]: 0;
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assign vga_g = ~blank_pipe[1] ? color[7:4] : 0;
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assign vga_b = ~blank_pipe[1] ? color[3:0] : 0;
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assign vga_hs = ~hsync_pipe[1];
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assign vga_vs = ~vsync_pipe[1];
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endmodule
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`default_nettype wire
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