68 lines
3.0 KiB
Systemverilog
68 lines
3.0 KiB
Systemverilog
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/* vga: Generate VGA display signals (1024 x 768 @ 60Hz)
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*
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* ---- HORIZONTAL ----- ------VERTICAL -----
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* Active Active
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* Freq Video FP Sync BP Video FP Sync BP
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* 640x480, 60Hz 25.175 640 16 96 48 480 11 2 31
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* 800x600, 60Hz 40.000 800 40 128 88 600 1 4 23
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* 1024x768, 60Hz 65.000 1024 24 136 160 768 3 6 29
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* 1280x1024, 60Hz 108.00 1280 48 112 248 768 1 3 38
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* 1280x720p 60Hz 75.25 1280 72 80 216 720 3 5 30
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* 1920x1080 60Hz 148.5 1920 88 44 148 1080 4 5 36
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*
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* change the clock frequency, front porches, sync's, and back porches to create
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* other screen resolutions
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*/
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module vga(
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input wire pixel_clk_in,
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output logic [10:0] hcount_out, // pixel number on current line
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output logic [9:0] vcount_out, // line number
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output logic vsync_out, hsync_out,
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output logic blank_out);
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parameter DISPLAY_WIDTH = 1024; // display width
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parameter DISPLAY_HEIGHT = 768; // number of lines
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parameter H_FP = 24; // horizontal front porch
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parameter H_SYNC_PULSE = 136; // horizontal sync
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parameter H_BP = 160; // horizontal back porch
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parameter V_FP = 3; // vertical front porch
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parameter V_SYNC_PULSE = 6; // vertical sync
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parameter V_BP = 29; // vertical back porch
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// horizontal: 1344 pixels total
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// display 1024 pixels per line
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logic hblank,vblank;
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logic hsyncon,hsyncoff,hreset,hblankon;
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assign hblankon = (hcount_out == (DISPLAY_WIDTH -1));
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assign hsyncon = (hcount_out == (DISPLAY_WIDTH + H_FP - 1)); //1047
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assign hsyncoff = (hcount_out == (DISPLAY_WIDTH + H_FP + H_SYNC_PULSE - 1)); // 1183
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assign hreset = (hcount_out == (DISPLAY_WIDTH + H_FP + H_SYNC_PULSE + H_BP - 1)); //1343
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// vertical: 806 lines total
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// display 768 lines
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logic vsyncon,vsyncoff,vreset,vblankon;
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assign vblankon = hreset & (vcount_out == (DISPLAY_HEIGHT - 1)); // 767
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assign vsyncon = hreset & (vcount_out == (DISPLAY_HEIGHT + V_FP - 1)); // 771
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assign vsyncoff = hreset & (vcount_out == (DISPLAY_HEIGHT + V_FP + V_SYNC_PULSE - 1)); // 777
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assign vreset = hreset & (vcount_out == (DISPLAY_HEIGHT + V_FP + V_SYNC_PULSE + V_BP - 1)); // 805
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// sync and blanking
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logic next_hblank,next_vblank;
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assign next_hblank = hreset ? 0 : hblankon ? 1 : hblank;
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assign next_vblank = vreset ? 0 : vblankon ? 1 : vblank;
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always_ff @(posedge pixel_clk_in) begin
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hcount_out <= hreset ? 0 : hcount_out + 1;
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hblank <= next_hblank;
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hsync_out <= hsyncon ? 0 : hsyncoff ? 1 : hsync_out; // active low
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vcount_out <= hreset ? (vreset ? 0 : vcount_out + 1) : vcount_out;
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vblank <= next_vblank;
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vsync_out <= vsyncon ? 0 : vsyncoff ? 1 : vsync_out; // active low
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blank_out <= next_vblank | (next_hblank & ~hreset);
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end
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endmodule |