38 lines
681 B
Systemverilog
38 lines
681 B
Systemverilog
`default_nettype none
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`timescale 1ns/1ps
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module playback_tb();
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logic clk;
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always begin
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#5;
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clk = !clk;
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end
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logic spike;
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logic [1:0] jet;
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logic [2:0] valentine;
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logic [3:0] ed;
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logic [4:0] ein;
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my_logic_analyzer_playback #(.MEM_FILE("capture.mem")) my_logic_analyzer_playback_inst (
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.clk(clk),
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.enable(1'b1),
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.spike(spike),
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.jet(jet),
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.valentine(valentine),
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.ed(ed),
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.ein(ein));
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initial begin
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clk = 0;
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$dumpfile("playback_tb.vcd");
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$dumpvars(0, playback_tb);
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#(450000*5);
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$finish();
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end
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endmodule
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`default_nettype wire |