58 lines
1.4 KiB
Verilog
58 lines
1.4 KiB
Verilog
/*
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This playback module was generated with Manta v0.0.5 on 23 Aug 2023 at 11:25:46 by fischerm
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If this breaks or if you've got dank formal verification memes, contact fischerm [at] mit.edu
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Provided under a GNU GPLv3 license. Go wild.
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Here's an example instantiation of the Manta module you configured, feel free to copy-paste
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this into your source!
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my_logic_analyzer_playback #(.MEM_FILE("capture.mem")) my_logic_analyzer_playback_inst (
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.clk(clk),
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.enable(1'b1),
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.spike(spike),
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.jet(jet),
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.valentine(valentine),
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.ed(ed),
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.ein(ein));
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*/
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module my_logic_analyzer_playback (
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input wire clk,
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input wire enable,
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output reg done,
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output reg spike,
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output reg [1:0] jet,
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output reg [2:0] valentine,
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output reg [3:0] ed,
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output reg [4:0] ein);
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parameter MEM_FILE = "";
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localparam SAMPLE_DEPTH = 1024;
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localparam TOTAL_PROBE_WIDTH = 15;
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reg [TOTAL_PROBE_WIDTH-1:0] capture [SAMPLE_DEPTH-1:0];
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reg [$clog2(SAMPLE_DEPTH)-1:0] addr;
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reg [TOTAL_PROBE_WIDTH-1:0] sample;
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assign done = (addr >= SAMPLE_DEPTH);
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initial begin
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$readmemb(MEM_FILE, capture, 0, SAMPLE_DEPTH-1);
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addr = 0;
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end
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always @(posedge clk) begin
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if (enable && !done) begin
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addr = addr + 1;
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sample = capture[addr];
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{ein, ed, valentine, jet, spike} = sample;
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end
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end
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endmodule |