Fischer Moseley e48f60e03a make downlink core export as just one verilog file

2023-02-05 10:22:54 -05:00

..

src

make downlink core export as just one verilog file

2023-02-05 10:22:54 -05:00

xdc

import from openILA

2023-02-04 12:43:00 -05:00

ila.json

merge + refactor

2023-02-04 18:53:52 -05:00

ila.yaml

merge + refactor

2023-02-04 18:53:52 -05:00

lab-bc.py

import from openILA

2023-02-04 12:43:00 -05:00