4 Commits

Author	SHA1	Message	Date
Fischer Moseley	c1620871cf	add lut memory and tests, still need to sort out pipelining	2023-03-14 16:24:56 -04:00
Fischer Moseley	e55d919098	add in bus architecture prototypes from the last few days	2023-03-14 16:24:56 -04:00
Fischer Moseley	523b5673bc	rename ila tests	2023-02-09 15:31:32 -05:00
Fischer Moseley	d2bcbe2418	import from openILA	2023-02-04 12:43:00 -05:00