diff --git a/.github/workflows/functional_simulation.yml b/.github/workflows/functional_sim.yml similarity index 71% rename from .github/workflows/functional_simulation.yml rename to .github/workflows/functional_sim.yml index 113a5a2..36f14ab 100644 --- a/.github/workflows/functional_simulation.yml +++ b/.github/workflows/functional_sim.yml @@ -1,4 +1,4 @@ -name: functional_simulation +name: functional_sim on: [push] jobs: all: @@ -6,4 +6,4 @@ jobs: steps: - uses: actions/checkout@v3 - run: sudo apt install iverilog - - run: make sim \ No newline at end of file + - run: make functional_sim \ No newline at end of file diff --git a/Makefile b/Makefile index 5f90228..8cbd23b 100644 --- a/Makefile +++ b/Makefile @@ -15,59 +15,59 @@ total_loc: find . -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.yml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs wc -l real_loc: - find src ${TB} -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs wc -l + find src test -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs wc -l -test: api_gen func_sim +test: auto_gen functional_sim # API Generation Tests -api_gen: - python3 test/api_gen/run_test.py +auto_gen: + python3 test/auto_gen/run_tests.py # Functional Simulation -func_sim: io_core_tb logic_analyzer_tb bit_fifo_tb bridge_rx_tb bridge_tx_tb fifo_tb lut_ram_tb uart_tb uart_tx_tb +functional_sim: io_core_tb logic_analyzer_tb bit_fifo_tb bridge_rx_tb bridge_tx_tb fifo_tb lut_ram_tb uart_tb uart_tx_tb io_core_tb: - iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/io_core_tb.sv + iverilog -g2012 -o sim.out -y src/manta test/functional_sim/io_core_tb.sv vvp sim.out rm sim.out logic_analyzer_tb: - iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/logic_analyzer_tb.sv + iverilog -g2012 -o sim.out -y src/manta test/functional_sim/logic_analyzer_tb.sv vvp sim.out rm sim.out bit_fifo_tb: - iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/bit_fifo_tb.sv + iverilog -g2012 -o sim.out -y src/manta test/functional_sim/bit_fifo_tb.sv vvp sim.out rm sim.out bridge_rx_tb: - iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/bridge_rx_tb.sv + iverilog -g2012 -o sim.out -y src/manta test/functional_sim/bridge_rx_tb.sv vvp sim.out rm sim.out bridge_tx_tb: - iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/bridge_tx_tb.sv + iverilog -g2012 -o sim.out -y src/manta test/functional_sim/bridge_tx_tb.sv vvp sim.out rm sim.out fifo_tb: - iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/fifo_tb.sv + iverilog -g2012 -o sim.out -y src/manta test/functional_sim/fifo_tb.sv vvp sim.out >> /dev/null # this one is noisy right now rm sim.out lut_ram_tb: - iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/lut_ram_tb.sv + iverilog -g2012 -o sim.out -y src/manta test/functional_sim/lut_ram_tb.sv vvp sim.out rm sim.out uart_tb: - iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/uart_tb.sv + iverilog -g2012 -o sim.out -y src/manta test/functional_sim/uart_tb.sv vvp sim.out rm sim.out uart_tx_tb: - iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/uart_tx_tb.sv + iverilog -g2012 -o sim.out -y src/manta test/functional_sim/uart_tx_tb.sv vvp sim.out rm sim.out diff --git a/src/manta/__init__.py b/src/manta/__init__.py index cf94ef6..c3fba5e 100644 --- a/src/manta/__init__.py +++ b/src/manta/__init__.py @@ -9,10 +9,7 @@ class UARTInterface: def __init__(self, config): # Obtain port. Try to automatically detect port if "auto" is specified assert "port" in config, "No serial port provided to UART core." - self.port = config["port"] - if config["port"] == "auto": - self.port = self.autodetect_port() # Check that clock frequency is provided and positive assert "clock_freq" in config, "Clock frequency not provided to UART core." @@ -42,6 +39,9 @@ class UARTInterface: self.verbose = config["verbose"] def open_port_if_not_alredy_open(self): + if self.port == "auto": + self.port = self.autodetect_port() + if not hasattr(self, "ser"): import serial self.ser = serial.Serial(self.port, self.baudrate) @@ -53,8 +53,8 @@ class UARTInterface: recognized_devices = [] for port in serial.tools.list_ports.comports(): if (port.vid == 0x403) and (port.pid == 0x6010): - recognized_devices.append(port) - + recognized_devices.append(port) + # board manufacturers seem to always make the 0th serial # interface on the FT2232 be for programming over JTAG, # and then the 1st to be for UART. as a result, we always diff --git a/test/api_gen/invalid_configs/0_mangled_yaml.yaml b/test/auto_gen/invalid_configs/0_mangled_yaml.yaml similarity index 100% rename from test/api_gen/invalid_configs/0_mangled_yaml.yaml rename to test/auto_gen/invalid_configs/0_mangled_yaml.yaml diff --git a/test/api_gen/invalid_configs/1_mangled_yaml.yaml b/test/auto_gen/invalid_configs/1_mangled_yaml.yaml similarity index 100% rename from test/api_gen/invalid_configs/1_mangled_yaml.yaml rename to test/auto_gen/invalid_configs/1_mangled_yaml.yaml diff --git a/test/api_gen/invalid_configs/2_mangled_yaml.yaml b/test/auto_gen/invalid_configs/2_mangled_yaml.yaml similarity index 100% rename from test/api_gen/invalid_configs/2_mangled_yaml.yaml rename to test/auto_gen/invalid_configs/2_mangled_yaml.yaml diff --git a/test/api_gen/run_test.py b/test/auto_gen/run_tests.py similarity index 82% rename from test/api_gen/run_test.py rename to test/auto_gen/run_tests.py index 366797a..3352553 100644 --- a/test/api_gen/run_test.py +++ b/test/auto_gen/run_tests.py @@ -7,8 +7,11 @@ from manta import Manta # Valid Configurations +# test that they make a python API without errors +# test that their verilog passes lint + print(" ==== Testing valid configurations ====") -valid_configs_path = 'test/api_gen/valid_configs/' +valid_configs_path = 'test/auto_gen/valid_configs/' for config_file in sorted(listdir(valid_configs_path)): caught_exception = None try: @@ -29,8 +32,10 @@ print('\n') # Invalid Configurations +# test that they throw errors when generating a python API + print(" ==== Testing invalid configurations ====") -invalid_configs_path = 'test/api_gen/invalid_configs/' +invalid_configs_path = 'test/auto_gen/invalid_configs/' for config_file in sorted(listdir(invalid_configs_path)): caught_exception = None try: diff --git a/test/api_gen/valid_configs/0_io_core.yaml b/test/auto_gen/valid_configs/0_io_core.yaml similarity index 100% rename from test/api_gen/valid_configs/0_io_core.yaml rename to test/auto_gen/valid_configs/0_io_core.yaml diff --git a/test/api_gen/valid_configs/1_logic_analyzer.yaml b/test/auto_gen/valid_configs/1_logic_analyzer.yaml similarity index 100% rename from test/api_gen/valid_configs/1_logic_analyzer.yaml rename to test/auto_gen/valid_configs/1_logic_analyzer.yaml diff --git a/test/api_gen/valid_configs/2_lut_ram.yaml b/test/auto_gen/valid_configs/2_lut_ram.yaml similarity index 100% rename from test/api_gen/valid_configs/2_lut_ram.yaml rename to test/auto_gen/valid_configs/2_lut_ram.yaml diff --git a/test/hdl_tb/bit_fifo_tb.sv b/test/functional_sim/bit_fifo_tb.sv similarity index 100% rename from test/hdl_tb/bit_fifo_tb.sv rename to test/functional_sim/bit_fifo_tb.sv diff --git a/test/hdl_tb/bridge_rx_tb.sv b/test/functional_sim/bridge_rx_tb.sv similarity index 100% rename from test/hdl_tb/bridge_rx_tb.sv rename to test/functional_sim/bridge_rx_tb.sv diff --git a/test/hdl_tb/bridge_tx_tb.sv b/test/functional_sim/bridge_tx_tb.sv similarity index 100% rename from test/hdl_tb/bridge_tx_tb.sv rename to test/functional_sim/bridge_tx_tb.sv diff --git a/test/hdl_tb/bus_fix_tb.sv b/test/functional_sim/bus_fix_tb.sv similarity index 100% rename from test/hdl_tb/bus_fix_tb.sv rename to test/functional_sim/bus_fix_tb.sv diff --git a/test/hdl_tb/fifo_tb.sv b/test/functional_sim/fifo_tb.sv similarity index 100% rename from test/hdl_tb/fifo_tb.sv rename to test/functional_sim/fifo_tb.sv diff --git a/test/hdl_tb/io_core_tb.sv b/test/functional_sim/io_core_tb.sv similarity index 100% rename from test/hdl_tb/io_core_tb.sv rename to test/functional_sim/io_core_tb.sv diff --git a/test/hdl_tb/logic_analyzer_tb.sv b/test/functional_sim/logic_analyzer_tb.sv similarity index 100% rename from test/hdl_tb/logic_analyzer_tb.sv rename to test/functional_sim/logic_analyzer_tb.sv diff --git a/test/hdl_tb/lut_ram_tb.sv b/test/functional_sim/lut_ram_tb.sv similarity index 100% rename from test/hdl_tb/lut_ram_tb.sv rename to test/functional_sim/lut_ram_tb.sv diff --git a/test/hdl_tb/uart_tb.sv b/test/functional_sim/uart_tb.sv similarity index 100% rename from test/hdl_tb/uart_tb.sv rename to test/functional_sim/uart_tb.sv diff --git a/test/hdl_tb/uart_tx_tb.sv b/test/functional_sim/uart_tx_tb.sv similarity index 100% rename from test/hdl_tb/uart_tx_tb.sv rename to test/functional_sim/uart_tx_tb.sv