From d1a772784a54656f2dc5505c4b758d25b248ada6 Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Wed, 6 Mar 2024 11:26:31 -0800
Subject: [PATCH] add environment.sh for tool paths and serial ports

---
 environment.sh                 | 11 +++++++++++
 test/test_io_core_hw.py        |  5 +++--
 test/test_logic_analyzer_hw.py |  5 +++--
 test/test_mem_core_hw.py       |  7 ++++---
 4 files changed, 21 insertions(+), 7 deletions(-)
 create mode 100644 environment.sh

diff --git a/environment.sh b/environment.sh
new file mode 100644
index 0000000..1c622d0
--- /dev/null
+++ b/environment.sh
@@ -0,0 +1,11 @@
+#!/usr/bin/env bash
+
+export VIVADO=/tools/Xilinx/Vivado/2023.1/bin/vivado
+
+export YOSYS=/tools/oss-cad-suite/bin/yosys
+export NEXTPNR_ICE40=/tools/oss-cad-suite/bin/nextpnr-ice40
+export ICEPACK=/tools/oss-cad-suite/bin/icepack
+export ICEPROG=/tools/oss-cad-suite/bin/iceprog
+
+export NEXYS4DDR_PORT=/dev/serial/by-id/usb-Digilent_Digilent_USB_Device_210292696307-if01-port0
+export ICESTICK_PORT=/dev/serial/by-id/usb-Lattice_Lattice_FTUSB_Interface_Cable-if01-port0
diff --git a/test/test_io_core_hw.py b/test/test_io_core_hw.py
index d40aada..c5ab941 100644
--- a/test/test_io_core_hw.py
+++ b/test/test_io_core_hw.py
@@ -5,6 +5,7 @@ from manta import Manta
 from manta.utils import *
 import pytest
 from random import getrandbits
+import os
 
 
 class IOCoreLoopbackTest(Elaboratable):
@@ -143,11 +144,11 @@ class IOCoreLoopbackTest(Elaboratable):
 
 @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
 def test_output_probe_initial_values_xilinx():
-    port = "/dev/serial/by-id/usb-Digilent_Digilent_USB_Device_210292696307-if01-port0"
+    port = os.environ["NEXYS4DDR_PORT"]
     IOCoreLoopbackTest(Nexys4DDRPlatform(), port).verify()
 
 
 @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed")
 def test_output_probe_initial_values_ice40():
-    port = "/dev/serial/by-id/usb-Lattice_Lattice_FTUSB_Interface_Cable-if01-port0"
+    port = os.environ["ICESTICK_PORT"]
     IOCoreLoopbackTest(ICEStickPlatform(), port).verify()
diff --git a/test/test_logic_analyzer_hw.py b/test/test_logic_analyzer_hw.py
index 8a25335..f82bec2 100644
--- a/test/test_logic_analyzer_hw.py
+++ b/test/test_logic_analyzer_hw.py
@@ -4,6 +4,7 @@ from amaranth_boards.icestick import ICEStickPlatform
 from manta import Manta
 from manta.utils import *
 import pytest
+import os
 
 
 class LogicAnalyzerCounterTest(Elaboratable):
@@ -78,11 +79,11 @@ class LogicAnalyzerCounterTest(Elaboratable):
 
 @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
 def test_logic_analyzer_core_xilinx():
-    port = "/dev/serial/by-id/usb-Digilent_Digilent_USB_Device_210292696307-if01-port0"
+    port = os.environ["NEXYS4DDR_PORT"]
     LogicAnalyzerCounterTest(Nexys4DDRPlatform(), port).verify()
 
 
 @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed")
 def test_logic_analyzer_core_ice40():
-    port = "/dev/serial/by-id/usb-Lattice_Lattice_FTUSB_Interface_Cable-if01-port0"
+    port = os.environ["ICESTICK_PORT"]
     LogicAnalyzerCounterTest(ICEStickPlatform(), port).verify()
diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py
index 9cb73f3..242e4c6 100644
--- a/test/test_mem_core_hw.py
+++ b/test/test_mem_core_hw.py
@@ -4,8 +4,9 @@ from amaranth_boards.icestick import ICEStickPlatform
 from manta import Manta
 from manta.utils import *
 import pytest
-from random import randint, getrandbits
+from random import getrandbits
 from math import ceil, log2
+import os
 
 """
 Fundamentally we want a function to generate a configuration (as a dictionary)
@@ -112,13 +113,13 @@ class MemoryCoreLoopbackTest(Elaboratable):
 
 @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
 def test_mem_core_xilinx():
-    port = "/dev/serial/by-id/usb-Digilent_Digilent_USB_Device_210292696307-if01-port0"
+    port = os.environ["NEXYS4DDR_PORT"]
     MemoryCoreLoopbackTest(Nexys4DDRPlatform(), 33, 1024, port).verify()
 
 
 @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed")
 def test_mem_core_ice40():
-    port = "/dev/serial/by-id/usb-Lattice_Lattice_FTUSB_Interface_Cable-if01-port0"
+    port = os.environ["ICESTICK_PORT"]
     MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 2, port).verify()
     MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 512, port).verify()
     MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 1024, port).verify()