From cef5e9318b74dd5308b24503d2ba038a64a42d5d Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Fri, 28 Apr 2023 00:20:27 -0400
Subject: [PATCH] flip i and j, and see the light

---
 Makefile                         | 2 +-
 src/manta/lut_mem_core/lut_mem.v | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index bb4f318..61c8763 100644
--- a/Makefile
+++ b/Makefile
@@ -86,7 +86,7 @@ bridge_tx_tb:
 	rm sim.out
 
 lut_mem_tb:
-	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/lut_mem_tb.sv
+	iverilog -g2012 -o sim.out -y src/manta/lut_mem_core test/functional_sim/lut_mem_tb.sv
 	vvp sim.out
 	rm sim.out
 
diff --git a/src/manta/lut_mem_core/lut_mem.v b/src/manta/lut_mem_core/lut_mem.v
index 6876fdd..7ba8335 100644
--- a/src/manta/lut_mem_core/lut_mem.v
+++ b/src/manta/lut_mem_core/lut_mem.v
@@ -21,7 +21,7 @@ module lut_mem (
     parameter DEPTH = 8;
     parameter BASE_ADDR = 0;
     parameter READ_ONLY = 0;
-    reg [DEPTH-1:0] mem [15:0];
+    reg [15:0] mem [DEPTH-1:0];
 
     always @(posedge clk) begin
         addr_o <= addr_i;