From ccc75270a88f672a86cbb7303299958ecf50774f Mon Sep 17 00:00:00 2001 From: Kenneth Wilke Date: Sun, 31 Mar 2024 23:17:03 -0500 Subject: [PATCH] Update getting_started.md MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I was working through using Manta for the first time, and the only bit that gave me a struggle so far was that I was expecting the `rst` signal to be active LOW. I thought this might be worth calling out in the documentation here. Awesome project btw, will definitely be using it more and try to contribute as I can! 😄 --- doc/getting_started.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/doc/getting_started.md b/doc/getting_started.md index 7494a49..70f900f 100644 --- a/doc/getting_started.md +++ b/doc/getting_started.md @@ -60,6 +60,8 @@ This Manta instance has an IO Core and a Logic Analyzer, each containing a numbe Lastly, we Manta can automatically generate a copy-pasteable Verilog snippet to instantiate Manta in your design by running `manta inst [config_file]`. For example, the following snippet is generated for the configuration above: +> Note: The reset signal, `rst`, is an active HIGH signal. + ```verilog manta manta_inst ( .clk(clk), @@ -73,4 +75,4 @@ manta manta_inst ( .larry(larry), .curly(curly), .moe(moe)); -``` \ No newline at end of file +```