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tweak lut_ram example

This commit is contained in:
Fischer Moseley 2023-03-23 18:24:29 -04:00
parent a57b5908f2
commit c85cc4d357
2 changed files with 20 additions and 7 deletions
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15
examples/nexys_a7/lut_ram/src/manta.v
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@ -2,7 +2,7 @@
`timescale 1ns/1ps `timescale 1ns/1ps
/* /*
This manta definition was generated on 14 Mar 2023 at 13:06:49 by fischerm This manta definition was generated on 23 Mar 2023 at 18:12:05 by fischerm
If this breaks or if you've got dank formal verification memes, If this breaks or if you've got dank formal verification memes,
please contact fischerm [at] mit.edu please contact fischerm [at] mit.edu
@ -10,6 +10,19 @@ please contact fischerm [at] mit.edu
Provided under a GNU GPLv3 license. Go wild. Provided under a GNU GPLv3 license. Go wild.
*/ */
/*
// Here's an example instantiation of the Manta module you configured,
// feel free to copy-paste this into your source!
manta manta_inst (
.clk(clk),
.rx(rx),
.tx(tx));
*/
module manta ( module manta (
input wire clk, input wire clk,

6
examples/nexys_a7/lut_ram/src/top_level.sv
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@ -13,20 +13,20 @@ module top_level (
output logic uart_rxd_out output logic uart_rxd_out
); );
manta manta ( manta manta_inst (
.clk(clk), .clk(clk),
.rx(uart_txd_in), .rx(uart_txd_in),
.tx(uart_rxd_out)); .tx(uart_rxd_out));
assign led = manta.brx_my_lut_ram_addr; assign led = manta_inst.brx_my_lut_ram_addr;
logic [6:0] cat; logic [6:0] cat;
assign {cg,cf,ce,cd,cc,cb,ca} = cat; assign {cg,cf,ce,cd,cc,cb,ca} = cat;
ssd ssd ( ssd ssd (
.clk_in(clk), .clk_in(clk),
.rst_in(btnc), .rst_in(btnc),
.val_in( (manta.my_lut_ram_btx_rdata << 16) | (manta.brx_my_lut_ram_wdata) ), .val_in( (manta_inst.my_lut_ram_btx_rdata << 16) | (manta_inst.brx_my_lut_ram_wdata) ),
.cat_out(cat), .cat_out(cat),
.an_out(an)); .an_out(an));