From c85cc4d3574e2d2d96d00249a2508dfe91380f4d Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Thu, 23 Mar 2023 18:24:29 -0400
Subject: [PATCH] tweak lut_ram example

---
 examples/nexys_a7/lut_ram/src/manta.v      | 19 ++++++++++++++++---
 examples/nexys_a7/lut_ram/src/top_level.sv |  8 ++++----
 2 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/examples/nexys_a7/lut_ram/src/manta.v b/examples/nexys_a7/lut_ram/src/manta.v
index 820d05e..2950045 100644
--- a/examples/nexys_a7/lut_ram/src/manta.v
+++ b/examples/nexys_a7/lut_ram/src/manta.v
@@ -2,7 +2,7 @@
 `timescale 1ns/1ps
 
 /*
-This manta definition was generated on 14 Mar 2023 at 13:06:49 by fischerm
+This manta definition was generated on 23 Mar 2023 at 18:12:05 by fischerm
 
 If this breaks or if you've got dank formal verification memes,
 please contact fischerm [at] mit.edu
@@ -10,6 +10,19 @@ please contact fischerm [at] mit.edu
 Provided under a GNU GPLv3 license. Go wild.
 */
 
+/*
+
+// Here's an example instantiation of the Manta module you configured,
+// feel free to copy-paste this into your source!
+
+manta manta_inst (
+    .clk(clk),
+
+    .rx(rx),
+    .tx(tx));
+
+*/
+
 module manta (
     input wire clk,
 
@@ -62,7 +75,7 @@ module manta (
 
     bridge_tx btx (
         .clk(clk),
-        
+
         .rdata_i(my_lut_ram_btx_rdata),
         .rw_i(my_lut_ram_btx_rw),
         .valid_i(my_lut_ram_btx_valid),
@@ -74,7 +87,7 @@ module manta (
     logic utx_btx_ready;
     logic btx_utx_valid;
     logic [7:0] btx_utx_data;
-    
+
     uart_tx #(.CLOCKS_PER_BAUD(868)) utx (
         .clk(clk),
 
diff --git a/examples/nexys_a7/lut_ram/src/top_level.sv b/examples/nexys_a7/lut_ram/src/top_level.sv
index a29ced6..c1d66c9 100644
--- a/examples/nexys_a7/lut_ram/src/top_level.sv
+++ b/examples/nexys_a7/lut_ram/src/top_level.sv
@@ -12,21 +12,21 @@ module top_level (
 	input wire uart_txd_in,
 	output logic uart_rxd_out
 	);
-	
-    manta manta (
+
+    manta manta_inst (
         .clk(clk),
 
         .rx(uart_txd_in),
         .tx(uart_rxd_out));
 
-    assign led = manta.brx_my_lut_ram_addr;
+    assign led = manta_inst.brx_my_lut_ram_addr;
 
     logic [6:0] cat;
 	assign {cg,cf,ce,cd,cc,cb,ca} = cat;
     ssd ssd (
         .clk_in(clk),
         .rst_in(btnc),
-        .val_in( (manta.my_lut_ram_btx_rdata << 16) | (manta.brx_my_lut_ram_wdata) ),
+        .val_in( (manta_inst.my_lut_ram_btx_rdata << 16) | (manta_inst.brx_my_lut_ram_wdata) ),
         .cat_out(cat),
         .an_out(an));