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manta
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meta: switch from black to ruff

This commit is contained in:
Fischer Moseley 2024-08-06 16:30:13 -07:00
parent ecfbdaa86b
commit b1caec9c57
7 changed files with 3 additions and 10 deletions
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2
.github/workflows/run_tests.yml vendored
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@ -28,7 +28,7 @@ jobs:
- name: Check formatting - name: Check formatting
run: | run: |
source venv/bin/activate source venv/bin/activate
python3 -m black . --check python3 -m ruff format --check
- name: Run tests - name: Run tests
run: | run: |

2
Makefile
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@ -3,7 +3,7 @@ test:
python3 -m pytest --cov python3 -m pytest --cov
format: format:
python3 -m black . python3 -m ruff format
clean: clean:
git clean -Xdf git clean -Xdf

2
README.md
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@ -4,7 +4,7 @@
![run_tests](https://github.com/fischermoseley/manta/actions/workflows/run_tests.yml/badge.svg) ![run_tests](https://github.com/fischermoseley/manta/actions/workflows/run_tests.yml/badge.svg)
![build_docs](https://github.com/fischermoseley/manta/actions/workflows/build_docs.yml/badge.svg) ![build_docs](https://github.com/fischermoseley/manta/actions/workflows/build_docs.yml/badge.svg)
[![License: GPL v3](https://img.shields.io/badge/License-GPLv3-blue.svg)](https://www.gnu.org/licenses/gpl-3.0) [![License: GPL v3](https://img.shields.io/badge/License-GPLv3-blue.svg)](https://www.gnu.org/licenses/gpl-3.0)
[![Code style: black](https://img.shields.io/badge/code%20style-black-000000.svg)](https://github.com/psf/black) [![Ruff](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/astral-sh/ruff/main/assets/badge/v2.json)](https://github.com/astral-sh/ruff)
Manta is a tool for getting information into and out of FPGAs over an interface like UART or Ethernet. It's primarily intended for debugging, but it's robust enough to be a simple, reliable transport layer between a FPGA and a host machine. It lets you configure a series of cores on a shared bus via a YAML or JSON file, and then provides a Python API to each core, along with vendor-agnostic Verilog HDL to instantiate them on your FPGA. Manta is a tool for getting information into and out of FPGAs over an interface like UART or Ethernet. It's primarily intended for debugging, but it's robust enough to be a simple, reliable transport layer between a FPGA and a host machine. It lets you configure a series of cores on a shared bus via a YAML or JSON file, and then provides a Python API to each core, along with vendor-agnostic Verilog HDL to instantiate them on your FPGA.

1
src/manta/logic_analyzer/playback.py
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@ -52,7 +52,6 @@ class LogicAnalyzerPlayback(Elaboratable):
# Assign the probe values by part-selecting from the data port # Assign the probe values by part-selecting from the data port
lower = 0 lower = 0
for p in reversed(self._probes): for p in reversed(self._probes):
# Set output probe to zero if we're not # Set output probe to zero if we're not
with m.If(self.valid): with m.If(self.valid):
m.d.comb += p.eq(read_port.data[lower : lower + len(p)]) m.d.comb += p.eq(read_port.data[lower : lower + len(p)])

1
src/manta/manta.py
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@ -28,7 +28,6 @@ class Manta(Elaboratable):
@classmethod @classmethod
def from_config(cls, config_path): def from_config(cls, config_path):
# Load config from YAML # Load config from YAML
extension = config_path.split(".")[-1] extension = config_path.split(".")[-1]
if extension not in ["yaml", "yml"]: if extension not in ["yaml", "yml"]:

2
test/test_mem_core_hw.py
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@ -78,7 +78,6 @@ class MemoryCoreLoopbackTest(Elaboratable):
if self.mode in ["bidirectional", "host_to_fpga"]: if self.mode in ["bidirectional", "host_to_fpga"]:
for addr in jumble(range(self.depth)): for addr in jumble(range(self.depth)):
# Write a random balue to a random bus address # Write a random balue to a random bus address
data = getrandbits(self.width) data = getrandbits(self.width)
self.manta.cores.mem.write(addr, data) self.manta.cores.mem.write(addr, data)
@ -92,7 +91,6 @@ class MemoryCoreLoopbackTest(Elaboratable):
if self.mode in ["bidirectional", "fpga_to_host"]: if self.mode in ["bidirectional", "fpga_to_host"]:
for addr in jumble(range(self.depth)): for addr in jumble(range(self.depth)):
# Write a random value to a random user address # Write a random value to a random user address
data = getrandbits(self.width) data = getrandbits(self.width)
self.write_user_side(addr, data) self.write_user_side(addr, data)

3
test/test_mem_core_sim.py
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@ -77,7 +77,6 @@ class MemoryCoreTests:
# random reads and writes in random orders # random reads and writes in random orders
for _ in range(5): for _ in range(5):
for addr in jumble(self.bus_addrs): for addr in jumble(self.bus_addrs):
operation = choice(["read", "write"]) operation = choice(["read", "write"])
if operation == "read": if operation == "read":
await self.verify_bus_side(addr) await self.verify_bus_side(addr)
@ -101,7 +100,6 @@ class MemoryCoreTests:
async def multi_user_write_then_multi_bus_reads(self): async def multi_user_write_then_multi_bus_reads(self):
# write-write-write then read-read-read # write-write-write then read-read-read
for user_addr in jumble(self.user_addrs): for user_addr in jumble(self.user_addrs):
# write a random number to the user side # write a random number to the user side
data = getrandbits(self.width) data = getrandbits(self.width)
await self.write_user_side(user_addr, data) await self.write_user_side(user_addr, data)
@ -193,7 +191,6 @@ class MemoryCoreTests:
# random reads and writes in random orders # random reads and writes in random orders
for _ in range(5): for _ in range(5):
for user_addr in jumble(self.user_addrs): for user_addr in jumble(self.user_addrs):
operation = choice(["read", "write"]) operation = choice(["read", "write"])
if operation == "read": if operation == "read":
await self.verify_user_side(user_addr) await self.verify_user_side(user_addr)