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add top-level interface ports to top-level declaration

This commit is contained in:
Fischer Moseley 2023-03-09 14:42:59 -05:00
parent a5518c1873
commit a6e7aa287d
1 changed files with 9 additions and 7 deletions
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16
src/manta/__init__.py
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@ -49,7 +49,7 @@ class UARTInterface:
# this should return the probes that we want to connect to top-level, but like as a string of verilog # this should return the probes that we want to connect to top-level, but like as a string of verilog
return """input wire rx, return """input wire rx,
output reg tx,""" output reg tx,"""
def rx_hdl_def(self): def rx_hdl_def(self):
uart_rx_def = pkgutil.get_data(__name__, "rx_uart.v").decode() uart_rx_def = pkgutil.get_data(__name__, "rx_uart.v").decode()
@ -65,7 +65,7 @@ class UARTInterface:
return f""" return f"""
rx_uart #(.CLOCKS_PER_BAUD({self.clocks_per_baud})) urx ( rx_uart #(.CLOCKS_PER_BAUD({self.clocks_per_baud})) urx (
.i_clk(clk), .i_clk(clk),
.i_uart_rx(tb_urx_rxd), .i_uart_rx(rx),
.o_wr(urx_brx_axiv), .o_wr(urx_brx_axiv),
.o_data(urx_brx_axid)); .o_data(urx_brx_axid));
@ -108,7 +108,7 @@ class UARTInterface:
.valid(btx_utx_valid), .valid(btx_utx_valid),
.ready(utx_btx_ready), .ready(utx_btx_ready),
.tx(utx_tb_tx));\n""" .tx(tx));\n"""
class IOCore: class IOCore:
@ -437,16 +437,18 @@ Provided under a GNU GPLv3 license. Go wild.
def generate_declaration(self): def generate_declaration(self):
# get all the top level connections for each module. # get all the top level connections for each module.
ports = [core.hdl_top_level_ports() for core in self.cores] interface_ports = self.interface.hdl_top_level_ports()
ports = "\n".join(ports)
print(ports) core_chain_ports = [core.hdl_top_level_ports() for core in self.cores]
core_chain_ports = "\n".join(core_chain_ports)
return f""" return f"""
module manta ( module manta (
input wire clk, input wire clk,
{ports}); {interface_ports}
{core_chain_ports});
""" """
def generate_interface_rx(self): def generate_interface_rx(self):