From 925fd915bee5b7f2c104c01c793adcd061002467 Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Sun, 16 Apr 2023 15:54:25 -0400
Subject: [PATCH] update simulation syntax for iverilog 11 compat

---
 test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv b/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv
index c0dee09..a7bbc44 100644
--- a/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv
+++ b/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv
@@ -50,8 +50,10 @@ task write_and_verify(
     assert(read_data == write_data) else $error("data read does not match data written!");
 endtask
 
-task read_all_reg();
-    string desc;
+task read_all_reg(
+    string desc
+    );
+
     for(int i = 0; i < (logic_analyzer_tb.la.block_mem.MAX_ADDR); i++) begin
 
         if(i == logic_analyzer_tb.la.fsm_registers.BASE_ADDR) desc = "FSM";