From 8e139bba3a56c1c4416f62372cc478e6f4a0ee1d Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Tue, 25 Apr 2023 00:32:28 -0400 Subject: [PATCH] add working l2 mac in hardware - need to fix ethertype to get scapy to play nice --- .../nexys_a7/lut_ram_ether/src/.gitignore | 1 + .../nexys_a7/lut_ram_ether/src/ethernet_rx.v | 2 +- .../nexys_a7/lut_ram_ether/src/ethernet_tx.v | 5 +- examples/nexys_a7/lut_ram_ether/src/manta.v | 123 ++++++++++++++++++ examples/nexys_a7/lut_ram_ether/src/ssd.v | 85 ++++++++++++ .../nexys_a7/lut_ram_ether/src/top_level.sv | 20 +++ .../nexys_a7/lut_ram_ether/xdc/top_level.xdc | 66 +++++----- src/manta/ethernet_rx.v | 2 +- src/manta/ethernet_tx.v | 5 +- 9 files changed, 272 insertions(+), 37 deletions(-) create mode 100644 examples/nexys_a7/lut_ram_ether/src/.gitignore create mode 100644 examples/nexys_a7/lut_ram_ether/src/manta.v create mode 100644 examples/nexys_a7/lut_ram_ether/src/ssd.v diff --git a/examples/nexys_a7/lut_ram_ether/src/.gitignore b/examples/nexys_a7/lut_ram_ether/src/.gitignore new file mode 100644 index 0000000..ab65942 --- /dev/null +++ b/examples/nexys_a7/lut_ram_ether/src/.gitignore @@ -0,0 +1 @@ +!manta.v \ No newline at end of file diff --git a/examples/nexys_a7/lut_ram_ether/src/ethernet_rx.v b/examples/nexys_a7/lut_ram_ether/src/ethernet_rx.v index aab553e..02676f9 100644 --- a/examples/nexys_a7/lut_ram_ether/src/ethernet_rx.v +++ b/examples/nexys_a7/lut_ram_ether/src/ethernet_rx.v @@ -33,7 +33,7 @@ module ethernet_rx ( assign addr_o = data[31:16]; assign wdata_o = data[15:0]; assign rw_o = (ethertype == 4); - assign valid_o = valid; + assign valid_o = valid && ((ethertype == 4) || (ethertype == 2)); endmodule diff --git a/examples/nexys_a7/lut_ram_ether/src/ethernet_tx.v b/examples/nexys_a7/lut_ram_ether/src/ethernet_tx.v index 3003886..b1f9725 100644 --- a/examples/nexys_a7/lut_ram_ether/src/ethernet_tx.v +++ b/examples/nexys_a7/lut_ram_ether/src/ethernet_tx.v @@ -12,10 +12,13 @@ module ethernet_tx( input wire valid_i ); + reg [15:0] data_buf = 0; + always @(posedge clk) if(~rw_i && valid_i) data_buf <= rdata_i; + mac_tx mtx ( .clk(clk), - .data(rdata_i), + .data(data_buf), .ethertype(16'h2), .start(~rw_i && valid_i), diff --git a/examples/nexys_a7/lut_ram_ether/src/manta.v b/examples/nexys_a7/lut_ram_ether/src/manta.v new file mode 100644 index 0000000..27329a4 --- /dev/null +++ b/examples/nexys_a7/lut_ram_ether/src/manta.v @@ -0,0 +1,123 @@ +`default_nettype none +`timescale 1ns/1ps +/* +This playback module was generated with Manta v0.0.0 on 24 Apr 2023 at 22:17:57 by fischerm + +If this breaks or if you've got dank formal verification memes, contact fischerm [at] mit.edu + +Provided under a GNU GPLv3 license. Go wild. + +Here's an example instantiation of the Manta module you configured, feel free to copy-paste +this into your source! + +manta manta_inst ( + .clk(clk), + + .rx(rx), + .tx(tx)); + +*/ + +module manta( + input wire clk, + + input wire crsdv, + input wire [1:0] rxd, + + output reg txen, + output reg [1:0] txd); + + ethernet_rx erx ( + .clk(clk), + + .crsdv(crsdv), + .rxd(rxd), + + .addr_o(brx_my_lut_ram_addr), + .wdata_o(brx_my_lut_ram_wdata), + .rw_o(brx_my_lut_ram_rw), + .valid_o(brx_my_lut_ram_valid)); + + reg [15:0] brx_my_lut_ram_addr; + reg [15:0] brx_my_lut_ram_wdata; + reg brx_my_lut_ram_rw; + reg brx_my_lut_ram_valid; + + + lut_ram #(.DEPTH(64)) my_lut_ram ( + .clk(clk), + + .addr_i(brx_my_lut_ram_addr), + .wdata_i(brx_my_lut_ram_wdata), + .rdata_i(), + .rw_i(brx_my_lut_ram_rw), + .valid_i(brx_my_lut_ram_valid), + + .addr_o(), + .wdata_o(), + .rdata_o(my_lut_ram_btx_rdata), + .rw_o(my_lut_ram_btx_rw), + .valid_o(my_lut_ram_btx_valid)); + + + reg [15:0] my_lut_ram_btx_rdata; + reg my_lut_ram_btx_rw; + reg my_lut_ram_btx_valid; + + ethernet_tx etx ( + .clk(clk), + + .txen(txen), + .txd(txd), + + .rdata_i(my_lut_ram_btx_rdata), + .rw_i(my_lut_ram_btx_rw), + .valid_i(my_lut_ram_btx_valid)); + +endmodule + + +module lut_ram ( + input wire clk, + + // input port + input wire [15:0] addr_i, + input wire [15:0] wdata_i, + input wire [15:0] rdata_i, + input wire rw_i, + input wire valid_i, + + // output port + output reg [15:0] addr_o, + output reg [15:0] wdata_o, + output reg [15:0] rdata_o, + output reg rw_o, + output reg valid_o); + + parameter DEPTH = 8; + parameter BASE_ADDR = 0; + parameter READ_ONLY = 0; + reg [DEPTH-1:0] mem [15:0]; + + always @(posedge clk) begin + addr_o <= addr_i; + wdata_o <= wdata_i; + rdata_o <= rdata_i; + rw_o <= rw_i; + valid_o <= valid_i; + rdata_o <= rdata_i; + + + if(valid_i) begin + // check if address is valid + if( (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + DEPTH - 1) ) begin + + // read/write + if (rw_i && !READ_ONLY) mem[addr_i - BASE_ADDR] <= wdata_i; + else rdata_o <= mem[addr_i - BASE_ADDR]; + end + end + end +endmodule + +`default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/lut_ram_ether/src/ssd.v b/examples/nexys_a7/lut_ram_ether/src/ssd.v new file mode 100644 index 0000000..dc27ee4 --- /dev/null +++ b/examples/nexys_a7/lut_ram_ether/src/ssd.v @@ -0,0 +1,85 @@ +module ssd( + input wire clk_in, + input wire rst_in, + input wire [31:0] val_in, + output reg[6:0] cat_out, + output reg[7:0] an_out); + + parameter COUNT_TO = 100000; + logic[7:0] segment_state; + logic[31:0] segment_counter; + logic [3:0] routed_vals; + logic [6:0] led_out; + + bto7s mbto7s (.x_in(routed_vals), .s_out(led_out)); + + assign cat_out = ~led_out; + assign an_out = ~segment_state; + + always @(*) begin + case(segment_state) + 8'b0000_0001: routed_vals = val_in[3:0]; + 8'b0000_0010: routed_vals = val_in[7:4]; + 8'b0000_0100: routed_vals = val_in[11:8]; + 8'b0000_1000: routed_vals = val_in[15:12]; + 8'b0001_0000: routed_vals = val_in[19:16]; + 8'b0010_0000: routed_vals = val_in[23:20]; + 8'b0100_0000: routed_vals = val_in[27:24]; + 8'b1000_0000: routed_vals = val_in[31:28]; + default: routed_vals = val_in[3:0]; + endcase + end + + always @(posedge clk_in) begin + if (rst_in) begin + segment_state <= 8'b0000_0001; + segment_counter <= 32'b0; + end + + else begin + if (segment_counter == COUNT_TO) begin + segment_counter <= 32'd0; + segment_state <= {segment_state[6:0],segment_state[7]}; + end else begin + segment_counter <= segment_counter +1; + end + end + end +endmodule + + +module bto7s( + input wire [3:0] x_in, + output reg [6:0] s_out); + + reg sa, sb, sc, sd, se, sf, sg; + assign s_out = {sg, sf, se, sd, sc, sb, sa}; + + // array of bits that are "one hot" with numbers 0 through 15 + reg [15:0] num; + + assign num[0] = ~x_in[3] && ~x_in[2] && ~x_in[1] && ~x_in[0]; + assign num[1] = ~x_in[3] && ~x_in[2] && ~x_in[1] && x_in[0]; + assign num[2] = x_in == 4'd2; + assign num[3] = x_in == 4'd3; + assign num[4] = x_in == 4'd4; + assign num[5] = x_in == 4'd5; + assign num[6] = x_in == 4'd6; + assign num[7] = x_in == 4'd7; + assign num[8] = x_in == 4'd8; + assign num[9] = x_in == 4'd9; + assign num[10] = x_in == 4'd10; + assign num[11] = x_in == 4'd11; + assign num[12] = x_in == 4'd12; + assign num[13] = x_in == 4'd13; + assign num[14] = x_in == 4'd14; + assign num[15] = x_in == 4'd15; + + assign sa = num[0] || num[2] || num[3] || num[5] || num[6] || num[7] || num[8] || num[9] || num[10] || num[12] ||num[14] ||num[15]; + assign sb = num[0] || num[1] || num[2] || num[3] || num[4] || num[7] || num[8] || num[9] || num[10] || num[13]; + assign sc = num[0] || num[1] || num[3] || num[4] || num[5] || num[6] || num[7] || num[8] || num[9] || num[10] || num[11] || num[13]; + assign sd = num[0] || num[2] || num[3] || num[5] || num[6] || num[8] || num[9] || num[11] || num[12] || num[13] || num[14]; + assign se = num[0] || num[2] || num[6] || num[8] || num[10] || num[11] || num[12] || num[13] || num[14] || num[15]; + assign sf = num[0] || num[4] || num[5] || num[6] || num[8] || num[9] || num[10] || num[11] || num[12] || num[14] || num[15]; + assign sg = num[2] || num[3] || num[4] || num[5] || num[6] || num[8] || num[9] || num[10] || num[11] || num[13] || num[14] ||num[15]; +endmodule diff --git a/examples/nexys_a7/lut_ram_ether/src/top_level.sv b/examples/nexys_a7/lut_ram_ether/src/top_level.sv index d7583b0..6b95885 100644 --- a/examples/nexys_a7/lut_ram_ether/src/top_level.sv +++ b/examples/nexys_a7/lut_ram_ether/src/top_level.sv @@ -8,6 +8,13 @@ module top_level ( input wire [15:0] sw, + output logic [15:0] led, + output logic ca, cb, cc, cd, ce, cf, cg, + output logic [7:0] an, + + output logic led16_r, + output logic led17_r, + output reg eth_refclk, output reg eth_rstn, @@ -27,6 +34,19 @@ module top_level ( assign eth_refclk = clk_50mhz; divider d (.clk(clk), .ethclk(clk_50mhz)); + assign led = manta_inst.brx_my_lut_ram_addr; + assign led16_r = manta_inst.brx_my_lut_ram_rw; + assign led17_r = manta_inst.brx_my_lut_ram_valid; + + logic [6:0] cat; + assign {cg,cf,ce,cd,cc,cb,ca} = cat; + ssd ssd ( + .clk_in(clk_50mhz), + .rst_in(btnc), + .val_in( {manta_inst.my_lut_ram_btx_rdata, manta_inst.brx_my_lut_ram_wdata} ), + .cat_out(cat), + .an_out(an)); + manta manta_inst ( .clk(clk_50mhz), diff --git a/examples/nexys_a7/lut_ram_ether/xdc/top_level.xdc b/examples/nexys_a7/lut_ram_ether/xdc/top_level.xdc index 7b112ac..350e0f6 100644 --- a/examples/nexys_a7/lut_ram_ether/xdc/top_level.xdc +++ b/examples/nexys_a7/lut_ram_ether/xdc/top_level.xdc @@ -37,51 +37,51 @@ set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] ## LEDs -# set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -# set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -# set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -# set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -# set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -# set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -# set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -# set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -# set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -# set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -# set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -# set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -# set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -# set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -# set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -# set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] # set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b # set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -# set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r +set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r # set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b # set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -# set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r +set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r ##7 segment display -# set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -# set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -# set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -# set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -# set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -# set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -# set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg +set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca +set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb +set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc +set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce +set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf +set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg # set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp -# set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -# set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -# set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -# set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -# set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -# set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -# set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -# set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] +set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] +set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] +set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] +set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] +set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] +set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] ##Buttons diff --git a/src/manta/ethernet_rx.v b/src/manta/ethernet_rx.v index aab553e..02676f9 100644 --- a/src/manta/ethernet_rx.v +++ b/src/manta/ethernet_rx.v @@ -33,7 +33,7 @@ module ethernet_rx ( assign addr_o = data[31:16]; assign wdata_o = data[15:0]; assign rw_o = (ethertype == 4); - assign valid_o = valid; + assign valid_o = valid && ((ethertype == 4) || (ethertype == 2)); endmodule diff --git a/src/manta/ethernet_tx.v b/src/manta/ethernet_tx.v index 3003886..b1f9725 100644 --- a/src/manta/ethernet_tx.v +++ b/src/manta/ethernet_tx.v @@ -12,10 +12,13 @@ module ethernet_tx( input wire valid_i ); + reg [15:0] data_buf = 0; + always @(posedge clk) if(~rw_i && valid_i) data_buf <= rdata_i; + mac_tx mtx ( .clk(clk), - .data(rdata_i), + .data(data_buf), .ethertype(16'h2), .start(~rw_i && valid_i),