ethernet: add individual methods for each flavor of MII
This commit is contained in:
Fischer Moseley
parent
ea6a264f0c
commit
8765dbec8a
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@ -56,6 +56,18 @@ Lastly, any additonal arguments provided in the `ethernet` section of the config
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Since Amaranth modules are Python objects, the configuration of the IO Core is given by the arguments given during initialization. See the documentation for the `EthernetInterface` [class constructor](#manta.EthernetInterface) below, as well as the Amaranth [examples](https://github.com/fischermoseley/manta/tree/main/examples/amaranth) in the repo.
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!!! note "Don't use `.eq()` when connecting to PHY IO pins!"
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The `EthernetInterface` has its own class methods for connecting to the IO pins routed to the PHY. This is necessary as some variations of the Media-Independent Interface used by Ethernet PHYs include bidirectional (ie, `inout`) signals, which require some special provisions in Amaranth. As a result these methods is used to connect the `EthernetInterface` to the Ethernet PHY, instead of using Amaranth's `.eq()`, as is done on the UARTInterface.
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For more information on the connections between your PHY and FPGA, please reference your PHY's datasheet, your development board's schematic, or [Wikipedia](https://wikipedia.org/wiki/Media-independent_interface) for more information.
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::: manta.EthernetInterface
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options:
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members: false
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members:
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- EthernetInterface
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- set_mii_phy_io
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- set_rmii_phy_io
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- set_gmii_phy_io
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- set_rgmii_phy_io
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- set_sgmii_phy_io
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@ -81,7 +81,7 @@ class EthernetIOCoreExample(Elaboratable):
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m.d.comb += eth_clk_io_buf.o.eq(ethclk.clk)
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# Wire Ethernet pins to the Manta instance
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self.manta.interface.set_phy_io(
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self.manta.interface.set_rmii_phy_io(
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rmii_clocks_ref_clk=ethclk.clk,
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rmii_rst_n=eth_pins.reset.io,
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rmii_rx_data=eth_pins.rxd.io,
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@ -4,7 +4,6 @@ from random import getrandbits
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from amaranth import *
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from amaranth.hdl import IOPort
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from manta.ethernet.phy_io_defs import phy_io_mapping
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from manta.ethernet.sink_bridge import UDPSinkBridge
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from manta.ethernet.source_bridge import UDPSourceBridge
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from manta.utils import *
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@ -161,23 +160,311 @@ class EthernetInterface(Elaboratable):
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return int("".join(octets), 2)
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def _define_phy_io(self, phy):
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phy_io = phy_io_mapping[phy]
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self._phy_io = [
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(p.dir, p.name, IOPort(width=p.width, name=p.name)) for p in phy_io
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mii_phys = ["LiteEthPHYMII"]
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rmii_phys = ["LiteEthPHYRMII"]
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gmii_phys = ["LiteEthPHYGMII", "LiteEthPHYGMIIMII"]
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rgmii_phys = ["LiteEthS7PHYRGMII", "LiteEthECP5PHYRGMII"]
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sgmii_phys = [
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"A7_1000BASEX",
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"A7_2500BASEX",
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"K7_1000BASEX",
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"K7_2500BASEX",
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"KU_1000BASEX",
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"KU_2500BASEX",
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"USP_GTH_1000BASEX",
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"USP_GTH_2500BASEX",
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"USP_GTY_1000BASEX",
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"USP_GTY_2500BASEX",
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]
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def set_phy_io(self, **kwargs):
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# Given the user's IO, create a list of tuples that can be passed to Instance
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# Only to be used in Amaranth-Native workflows!
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if phy in mii_phys:
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self.set_mii_phy_io(
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mii_clocks_rx=IOPort(name="mii_clocks_rx", width=1),
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mii_clocks_tx=IOPort(name="mii_clocks_tx", width=1),
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mii_rst_n=IOPort(name="mii_rst_n", width=1),
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mii_mdio=IOPort(name="mii_mdio", width=1),
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mii_mdc=IOPort(name="mii_mdc", width=1),
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mii_rx_dv=IOPort(name="mii_rx_dv", width=1),
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mii_rx_er=IOPort(name="mii_rx_er", width=1),
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mii_rx_data=IOPort(name="mii_rx_data", width=4),
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mii_tx_en=IOPort(name="mii_tx_en", width=1),
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mii_tx_data=IOPort(name="mii_tx_data", width=4),
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mii_col=IOPort(name="mii_col", width=1),
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mii_crs=IOPort(name="mii_crs", width=1),
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)
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all_phy_io = phy_io_mapping.values()
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all_io_definitions = [io for phy_io in all_phy_io for io in phy_io]
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find_io_def = lambda name: next(
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(iod for iod in all_io_definitions if iod.name == name), None
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)
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elif phy in rmii_phys:
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self.set_rmii_phy_io(
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rmii_clocks_ref_clk=IOPort(name="rmii_clocks_ref_clk", width=1),
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rmii_rst_n=IOPort(name="rmii_rst_n", width=1),
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rmii_rx_data=IOPort(name="rmii_rx_data", width=2),
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rmii_crs_dv=IOPort(name="rmii_crs_dv", width=1),
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rmii_tx_en=IOPort(name="rmii_tx_en", width=1),
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rmii_tx_data=IOPort(name="rmii_tx_data", width=2),
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rmii_mdc=IOPort(name="rmii_mdc", width=1),
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rmii_mdio=IOPort(name="rmii_mdio", width=1),
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)
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self._phy_io = [(find_io_def(k).dir, k, v) for k, v in kwargs.items()]
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elif phy in gmii_phys:
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self.set_gmii_phy_io(
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gmii_clocks_tx=IOPort(name="gmii_clocks_tx", width=1),
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gmii_clocks_gtx=IOPort(name="gmii_clocks_gtx", width=1),
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gmii_clocks_rx=IOPort(name="gmii_clocks_rx", width=1),
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gmii_rst_n=IOPort(name="gmii_rst_n", width=1),
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gmii_int_n=IOPort(name="gmii_int_n", width=1),
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gmii_mdio=IOPort(name="gmii_mdio", width=1),
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gmii_mdc=IOPort(name="gmii_mdc", width=1),
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gmii_rx_dv=IOPort(name="gmii_rx_dv", width=1),
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gmii_rx_er=IOPort(name="gmii_rx_er", width=1),
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gmii_rx_data=IOPort(name="gmii_rx_data", width=8),
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gmii_tx_en=IOPort(name="gmii_tx_en", width=1),
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gmii_tx_er=IOPort(name="gmii_tx_er", width=1),
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gmii_tx_data=IOPort(name="gmii_tx_data", width=8),
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gmii_col=IOPort(name="gmii_col", width=1),
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gmii_crs=IOPort(name="gmii_crs", width=1),
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)
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elif phy in rgmii_phys:
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self.set_rgmii_phy_io(
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rgmii_clocks_tx=IOPort(name="rgmii_clocks_tx", width=1),
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rgmii_clocks_rx=IOPort(name="rgmii_clocks_rx", width=1),
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rgmii_rst_n=IOPort(name="rgmii_rst_n", width=1),
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rgmii_int_n=IOPort(name="rgmii_int_n", width=1),
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rgmii_mdio=IOPort(name="rgmii_mdio", width=1),
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rgmii_mdc=IOPort(name="rgmii_mdc", width=1),
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rgmii_rx_ctl=IOPort(name="rgmii_rx_ctl", width=1),
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rgmii_rx_data=IOPort(name="rgmii_rx_data", width=4),
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rgmii_tx_ctl=IOPort(name="rgmii_tx_ctl", width=1),
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rgmii_tx_data=IOPort(name="rgmii_tx_data", width=4),
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)
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elif phy in sgmii_phys:
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self.set_sgmii_phy_io(
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sgmii_refclk=IOPort(name="sgmii_refclk", width=1),
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sgmii_rst=IOPort(name="sgmii_rst", width=1),
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sgmii_txp=IOPort(name="sgmii_txp", width=1),
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sgmii_txn=IOPort(name="sgmii_txn", width=1),
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sgmii_rxp=IOPort(name="sgmii_rxp", width=1),
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sgmii_rxn=IOPort(name="sgmii_rxn", width=1),
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sgmii_link_up=IOPort(name="sgmii_link_up", width=1),
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)
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def set_mii_phy_io(
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self,
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mii_clocks_tx,
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mii_clocks_rx,
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mii_rst_n,
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mii_mdio,
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mii_mdc,
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mii_rx_dv,
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mii_rx_er,
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mii_rx_data,
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mii_tx_en,
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mii_tx_data,
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mii_col,
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mii_crs,
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):
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"""
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Sets the signals used to connect to a MII PHY in an Amarnath-native
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design.
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Args:
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mii_clocks_tx (IOPort): Transmit Clock
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mii_clocks_rx (IOPort): Receive Clock
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mii_rst_n (IOPort): PHY Reset
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mii_mdio (IOPort): Management Data
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mii_mdc (IOPort): Management Data Clock
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mii_rx_dv (IOPort): Receive Data Valid
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mii_rx_er (IOPort): Recieve Error
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mii_rx_data (IOPort): Receive Data
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mii_tx_en (IOPort): Transmit Enable
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mii_tx_data (IOPort): Transmit Data
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mii_col (IOPort): Collision Detect
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mii_crs (IOPort): Carrier Sense
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"""
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self._phy_io = [
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("i", "mii_clocks_tx", mii_clocks_tx),
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("i", "mii_clocks_rx", mii_clocks_rx),
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("o", "mii_rst_n", mii_rst_n),
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("io", "mii_mdio", mii_mdio),
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("o", "mii_mdc", mii_mdc),
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("i", "mii_rx_dv", mii_rx_dv),
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("i", "mii_rx_er", mii_rx_er),
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("i", "mii_rx_data", mii_rx_data),
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("o", "mii_tx_en", mii_tx_en),
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("o", "mii_tx_data", mii_tx_data),
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("i", "mii_col", mii_col),
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("i", "mii_crs", mii_crs),
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]
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def set_rmii_phy_io(
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self,
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rmii_clocks_ref_clk,
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rmii_rst_n,
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rmii_rx_data,
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rmii_crs_dv,
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rmii_tx_en,
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rmii_tx_data,
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rmii_mdc,
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rmii_mdio,
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):
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"""
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Sets the signals used to connect to a RMII PHY in an Amarnath-native
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design.
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Args:
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rmii_clocks_ref_clk (IOPort): Reference Clock
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rmii_rst_n (IOPort): PHY Reset
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rmii_rx_data (IOPort): Receive Data
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rmii_crs_dv (IOPort): Carrier Sense and Receive Data Valid, multiplexed
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rmii_tx_en (IOPort): Transmit Enable
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rmii_tx_data (IOPort): Transmit Data
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rmii_mdc (IOPort): Management Data Clock
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rmii_mdio (IOPort): Management Data
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"""
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self._phy_io = [
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("i", "rmii_clocks_ref_clk", rmii_clocks_ref_clk),
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("o", "rmii_rst_n", rmii_rst_n),
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("i", "rmii_rx_data", rmii_rx_data),
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("i", "rmii_crs_dv", rmii_crs_dv),
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("o", "rmii_tx_en", rmii_tx_en),
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("o", "rmii_tx_data", rmii_tx_data),
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("o", "rmii_mdc", rmii_mdc),
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("io", "rmii_mdio", rmii_mdio),
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]
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def set_gmii_phy_io(
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self,
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gmii_clocks_tx,
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gmii_clocks_gtx,
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gmii_clocks_rx,
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gmii_rst_n,
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gmii_int_n,
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gmii_mdio,
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gmii_mdc,
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gmii_rx_dv,
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gmii_rx_er,
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gmii_rx_data,
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gmii_tx_en,
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gmii_tx_er,
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gmii_tx_data,
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gmii_col,
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gmii_crs,
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):
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"""
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Sets the signals used to connect to a GMII PHY in an Amarnath-native
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design.
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Args:
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gmii_clocks_tx (IOPort): Clock for 10/100 Mbit/s signals.
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gmii_clocks_gtx (IOPort): Clock for gigabit transmit signals
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gmii_clocks_rx (IOPort): Received Clock signal
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gmii_rst_n (IOPort): PHY Reset
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gmii_int_n (IOPort): PHY Interrupt
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gmii_mdio (IOPort): Management Data
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gmii_mdc (IOPort): Management Data Clock
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gmii_rx_dv (IOPort): Receive Data Valid
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gmii_rx_er (IOPort): Receive Error
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gmii_rx_data (IOPort): Receive Data
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gmii_tx_en (IOPort): Transmit Enable
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gmii_tx_er (IOPort): Transmit Error
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gmii_tx_data (IOPort): Transmit Data
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gmii_col (IOPort): Collision Detect
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gmii_crs (IOPort): Carrier Sense
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"""
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self._phy_io = [
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("i", "gmii_clocks_tx", gmii_clocks_tx),
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("o", "gmii_clocks_gtx", gmii_clocks_gtx),
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("i", "gmii_clocks_rx", gmii_clocks_rx),
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("o", "gmii_rst_n", gmii_rst_n),
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("i", "gmii_int_n", gmii_int_n),
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("io", "gmii_mdio", gmii_mdio),
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("o", "gmii_mdc", gmii_mdc),
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("i", "gmii_rx_dv", gmii_rx_dv),
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("i", "gmii_rx_er", gmii_rx_er),
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("i", "gmii_rx_data", gmii_rx_data),
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("o", "gmii_tx_en", gmii_tx_en),
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("o", "gmii_tx_er", gmii_tx_er),
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("o", "gmii_tx_data", gmii_tx_data),
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("i", "gmii_col", gmii_col),
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("i", "gmii_crs", gmii_crs),
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]
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def set_rgmii_phy_io(
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self,
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rgmii_clocks_tx,
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rgmii_clocks_rx,
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rgmii_rst_n,
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rgmii_int_n,
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rgmii_mdio,
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rgmii_mdc,
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rgmii_rx_ctl,
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rgmii_rx_data,
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rgmii_tx_ctl,
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rgmii_tx_data,
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):
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"""
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Sets the signals used to connect to a RGMII PHY in an Amarnath-native
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design.
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Args:
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rgmii_clocks_tx (IOPort): Transmit Clock
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rgmii_clocks_rx (IOPort): Receive Clock
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rgmii_rst_n (IOPort): PHY Reset
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rgmii_int_n (IOPort): PHY Interrupt
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rgmii_mdio (IOPort): Management Data
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rgmii_mdc (IOPort): Management Data Clock
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rgmii_rx_ctl (IOPort): Receive Error and Receive Data Valid, multiplexed
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rgmii_rx_data (IOPort): Receive Data
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rgmii_tx_ctl (IOPort): Transmit Enable and Transmit Error, multiplexed
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rgmii_tx_data (IOPort): Transmit Data
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"""
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self._phy_io = [
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("o", "rgmii_clocks_tx", rgmii_clocks_tx),
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("i", "rgmii_clocks_rx", rgmii_clocks_rx),
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("o", "rgmii_rst_n", rgmii_rst_n),
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("i", "rgmii_int_n", rgmii_int_n),
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("io", "rgmii_mdio", rgmii_mdio),
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("o", "rgmii_mdc", rgmii_mdc),
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("i", "rgmii_rx_ctl", rgmii_rx_ctl),
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("i", "rgmii_rx_data", rgmii_rx_data),
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("o", "rgmii_tx_ctl", rgmii_tx_ctl),
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("o", "rgmii_tx_data", rgmii_tx_data),
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]
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def set_sgmii_phy_io(
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self,
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sgmii_refclk,
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sgmii_rst,
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sgmii_txp,
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sgmii_txn,
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sgmii_rxp,
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sgmii_rxn,
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sgmii_link_up,
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):
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"""
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Sets the signals used to connect to a SGMII PHY in an Amarnath-native
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design.
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Args:
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sgmii_refclk (IOPort): Reference Clock
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sgmii_rst (IOPort): PHY Reset
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sgmii_txp (IOPort): Transmit Data (Differential)
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sgmii_txn (IOPort): Transmit Data (Differential)
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sgmii_rxp (IOPort): Receive Data (Differential)
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sgmii_rxn (IOPort): Receive Data (Differential)
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sgmii_link_up (IOPort): Link Status
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"""
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self._phy_io = [
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("i", "sgmii_refclk", sgmii_refclk),
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("i", "sgmii_rst", sgmii_rst),
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("o", "sgmii_txp", sgmii_txp),
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("o", "sgmii_txn", sgmii_txn),
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("i", "sgmii_rxp", sgmii_rxp),
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("i", "sgmii_rxn", sgmii_rxn),
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("o", "sgmii_link_up", sgmii_link_up),
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]
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def elaborate(self, platform):
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m = Module()
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@ -1,101 +0,0 @@
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from dataclasses import dataclass
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@dataclass
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class IODefinition:
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dir: str
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name: str
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width: int
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mii_phy_io = [
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IODefinition("i", "mii_clocks_tx", 1),
|
||||
IODefinition("i", "mii_clocks_rx", 1),
|
||||
IODefinition("o", "mii_rst_n", 1),
|
||||
IODefinition("io", "mii_mdio", 1),
|
||||
IODefinition("o", "mii_mdc", 1),
|
||||
IODefinition("i", "mii_rx_dv", 1),
|
||||
IODefinition("i", "mii_rx_er", 1),
|
||||
IODefinition("i", "mii_rx_data", 4),
|
||||
IODefinition("o", "mii_tx_en", 1),
|
||||
IODefinition("o", "mii_tx_data", 4),
|
||||
IODefinition("i", "mii_col", 1),
|
||||
IODefinition("i", "mii_crs", 1),
|
||||
]
|
||||
|
||||
rmii_phy_io = [
|
||||
IODefinition("i", "rmii_clocks_ref_clk", 1),
|
||||
IODefinition("o", "rmii_rst_n", 1),
|
||||
IODefinition("i", "rmii_rx_data", 2),
|
||||
IODefinition("i", "rmii_crs_dv", 1),
|
||||
IODefinition("o", "rmii_tx_en", 1),
|
||||
IODefinition("o", "rmii_tx_data", 2),
|
||||
IODefinition("o", "rmii_mdc", 1),
|
||||
IODefinition("io", "rmii_mdio", 1),
|
||||
]
|
||||
|
||||
gmii_phy_io = [
|
||||
IODefinition("i", "gmii_clocks_tx", 1),
|
||||
IODefinition("o", "gmii_clocks_gtx", 1),
|
||||
IODefinition("i", "gmii_clocks_rx", 1),
|
||||
IODefinition("o", "gmii_rst_n", 1),
|
||||
IODefinition("i", "gmii_int_n", 1),
|
||||
IODefinition("io", "gmii_mdio", 1),
|
||||
IODefinition("o", "gmii_mdc", 1),
|
||||
IODefinition("i", "gmii_rx_dv", 1),
|
||||
IODefinition("i", "gmii_rx_er", 1),
|
||||
IODefinition("i", "gmii_rx_data", 8),
|
||||
IODefinition("o", "gmii_tx_en", 1),
|
||||
IODefinition("o", "gmii_tx_er", 1),
|
||||
IODefinition("o", "gmii_tx_data", 8),
|
||||
IODefinition("i", "gmii_col", 1),
|
||||
IODefinition("i", "gmii_crs", 1),
|
||||
]
|
||||
|
||||
rgmii_phy_io = [
|
||||
IODefinition("o", "rgmii_clocks_tx", 1),
|
||||
IODefinition("i", "rgmii_clocks_rx", 1),
|
||||
IODefinition("o", "rgmii_rst_n", 1),
|
||||
IODefinition("i", "rgmii_int_n", 1),
|
||||
IODefinition("io", "rgmii_mdio", 1),
|
||||
IODefinition("o", "rgmii_mdc", 1),
|
||||
IODefinition("i", "rgmii_rx_ctl", 1),
|
||||
IODefinition("i", "rgmii_rx_data", 4),
|
||||
IODefinition("o", "rgmii_tx_ctl", 1),
|
||||
IODefinition("o", "rgmii_tx_data", 4),
|
||||
]
|
||||
|
||||
sgmii_phy_io = [
|
||||
IODefinition("i", "sgmii_refclk", 1),
|
||||
IODefinition("i", "sgmii_rst", 1),
|
||||
IODefinition("o", "sgmii_txp", 1),
|
||||
IODefinition("o", "sgmii_txn", 1),
|
||||
IODefinition("i", "sgmii_rxp", 1),
|
||||
IODefinition("i", "sgmii_rxn", 1),
|
||||
IODefinition("o", "sgmii_link_up", 1),
|
||||
]
|
||||
|
||||
|
||||
phy_io_mapping = {
|
||||
# MII
|
||||
"LiteEthPHYMII": mii_phy_io,
|
||||
# RMII
|
||||
"LiteEthPHYRMII": rmii_phy_io,
|
||||
# GMII
|
||||
"LiteEthPHYGMII": gmii_phy_io,
|
||||
"LiteEthPHYGMIIMII": gmii_phy_io,
|
||||
# RGMII
|
||||
"LiteEthS7PHYRGMII": rgmii_phy_io,
|
||||
"LiteEthECP5PHYRGMII": rgmii_phy_io,
|
||||
# SGMII
|
||||
"A7_1000BASEX": sgmii_phy_io,
|
||||
"A7_2500BASEX": sgmii_phy_io,
|
||||
"K7_1000BASEX": sgmii_phy_io,
|
||||
"K7_2500BASEX": sgmii_phy_io,
|
||||
"KU_1000BASEX": sgmii_phy_io,
|
||||
"KU_2500BASEX": sgmii_phy_io,
|
||||
"USP_GTH_1000BASEX": sgmii_phy_io,
|
||||
"USP_GTH_2500BASEX": sgmii_phy_io,
|
||||
"USP_GTY_1000BASEX": sgmii_phy_io,
|
||||
"USP_GTY_2500BASEX": sgmii_phy_io,
|
||||
}
|
||||
|
|
@ -73,7 +73,7 @@ class EthernetMemoryCoreTest(Elaboratable):
|
|||
m.d.comb += eth_clk_io_buf.o.eq(ethclk.clk)
|
||||
|
||||
# Wire Ethernet pins to the Manta instance
|
||||
self.manta.interface.set_phy_io(
|
||||
self.manta.interface.set_rmii_phy_io(
|
||||
rmii_clocks_ref_clk=ethclk.clk,
|
||||
rmii_rst_n=eth_pins.reset.io,
|
||||
rmii_rx_data=eth_pins.rxd.io,
|
||||
|
|
|
|||
Loading…
Reference in New Issue