uart: fix bit-slicing bug in StreamUnpacker

2026-03-07 22:15:10 -07:00 · 2026-03-07 22:15:10 -07:00 · 776d465ef2
parent b1643b3075
commit 776d465ef2
1 changed files with 1 additions and 1 deletions
--- a/src/manta/uart/stream_unpacker.py
+++ b/src/manta/uart/stream_unpacker.py
@ -49,7 +49,7 @@ class StreamUnpacker(wiring.Component):

                # if not done, clock out next byte
                with m.Else():
-                    m.d.sync += self.source.data.eq(buf[8:])
+                    m.d.sync += self.source.data.eq(buf[:8])
                    m.d.sync += buf.eq(buf >> 8)
                    m.d.sync += count.eq(count + 1)