From 776d465ef2f83bf83be27cd98b82a2b274390286 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sat, 7 Mar 2026 22:15:10 -0700 Subject: [PATCH] uart: fix bit-slicing bug in StreamUnpacker --- src/manta/uart/stream_unpacker.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/manta/uart/stream_unpacker.py b/src/manta/uart/stream_unpacker.py index dbd626c..c03fff5 100644 --- a/src/manta/uart/stream_unpacker.py +++ b/src/manta/uart/stream_unpacker.py @@ -49,7 +49,7 @@ class StreamUnpacker(wiring.Component): # if not done, clock out next byte with m.Else(): - m.d.sync += self.source.data.eq(buf[8:]) + m.d.sync += self.source.data.eq(buf[:8]) m.d.sync += buf.eq(buf >> 8) m.d.sync += count.eq(count + 1)