luke
/
manta
mirror of https://github.com/fischermoseley/manta.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

uart: fix (another) bit-slicing bug in StreamUnpacker

This commit is contained in:
Fischer Moseley 2026-03-08 21:14:42 -06:00
parent 3b3ff35fdd
commit 6888b4ded5
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/manta/uart/stream_unpacker.py
View File

@ -30,7 +30,7 @@ class StreamUnpacker(wiring.Component):
m.d.sync += last.eq(self.sink.last)
m.d.sync += idle.eq(0)
m.d.sync += self.source.data.eq(self.sink.data[:7])
m.d.sync += self.source.data.eq(self.sink.data[:8])
m.d.sync += self.source.valid.eq(1)
m.d.sync += count.eq(0)