From 6888b4ded5313fdd2bb3af034f8226b97d242821 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 8 Mar 2026 21:14:42 -0600 Subject: [PATCH] uart: fix (another) bit-slicing bug in StreamUnpacker --- src/manta/uart/stream_unpacker.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/manta/uart/stream_unpacker.py b/src/manta/uart/stream_unpacker.py index c03fff5..7423362 100644 --- a/src/manta/uart/stream_unpacker.py +++ b/src/manta/uart/stream_unpacker.py @@ -30,7 +30,7 @@ class StreamUnpacker(wiring.Component): m.d.sync += last.eq(self.sink.last) m.d.sync += idle.eq(0) - m.d.sync += self.source.data.eq(self.sink.data[:7]) + m.d.sync += self.source.data.eq(self.sink.data[:8]) m.d.sync += self.source.valid.eq(1) m.d.sync += count.eq(0)