uart: remove unused receive and transmit bridges
This commit is contained in:
Fischer Moseley
parent
52b3474655
commit
67dbac4a81
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@ -1,139 +0,0 @@
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from amaranth import *
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from amaranth.lib.data import ArrayLayout
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from amaranth.lib.enum import IntEnum
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class States(IntEnum):
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IDLE = 0
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READ = 1
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WRITE = 2
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class ReceiveBridge(Elaboratable):
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"""
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A module for bridging the stream of bytes from the UARTReceiver module to
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Manta's internal bus.
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"""
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def __init__(self):
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# Top-Level Ports
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self.data_i = Signal(8)
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self.valid_i = Signal()
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self.addr_o = Signal(16)
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self.data_o = Signal(16)
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self.rw_o = Signal()
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self.valid_o = Signal()
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# Internal Signals
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self._buffer = Signal(ArrayLayout(4, 8))
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self._state = Signal(States)
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self._byte_num = Signal(4)
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self._is_eol = Signal()
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self._is_ascii_hex = Signal()
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self._from_ascii_hex = Signal(8)
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def _drive_ascii_signals(self, m):
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# Decode 0-9
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with m.If((self.data_i >= 0x30) & (self.data_i <= 0x39)):
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m.d.comb += self._is_ascii_hex.eq(1)
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m.d.comb += self._from_ascii_hex.eq(self.data_i - 0x30)
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# Decode A-F
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with m.Elif((self.data_i >= 0x41) & (self.data_i <= 0x46)):
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m.d.comb += self._is_ascii_hex.eq(1)
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m.d.comb += self._from_ascii_hex.eq(self.data_i - 0x41 + 10)
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with m.Else():
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m.d.comb += self._is_ascii_hex.eq(0)
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m.d.comb += self._from_ascii_hex.eq(0)
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with m.If((self.data_i == ord("\r")) | (self.data_i == ord("\n"))):
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m.d.comb += self._is_eol.eq(1)
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with m.Else():
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m.d.comb += self._is_eol.eq(0)
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def _drive_output_bus(self, m):
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with m.If(
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(self._state == States.READ) & (self._byte_num == 4) & (self._is_eol)
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):
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m.d.comb += self.addr_o.eq(
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Cat(self._buffer[3], self._buffer[2], self._buffer[1], self._buffer[0])
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)
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m.d.comb += self.data_o.eq(0)
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m.d.comb += self.valid_o.eq(1)
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m.d.comb += self.rw_o.eq(0)
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with m.Elif(
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(self._state == States.WRITE) & (self._byte_num == 8) & (self._is_eol)
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):
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m.d.comb += self.addr_o.eq(
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Cat(self._buffer[3], self._buffer[2], self._buffer[1], self._buffer[0])
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)
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m.d.comb += self.data_o.eq(
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Cat(self._buffer[7], self._buffer[6], self._buffer[5], self._buffer[4])
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)
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m.d.comb += self.valid_o.eq(1)
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m.d.comb += self.rw_o.eq(1)
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with m.Else():
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m.d.comb += self.addr_o.eq(0)
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m.d.comb += self.data_o.eq(0)
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m.d.comb += self.rw_o.eq(0)
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m.d.comb += self.valid_o.eq(0)
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def _drive_fsm(self, m):
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with m.If(self.valid_i):
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with m.If(self._state == States.IDLE):
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m.d.sync += self._byte_num.eq(0)
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with m.If(self.data_i == ord("R")):
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m.d.sync += self._state.eq(States.READ)
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with m.Elif(self.data_i == ord("W")):
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m.d.sync += self._state.eq(States.WRITE)
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with m.If(self._state == States.READ):
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# buffer bytes if we don't have enough
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with m.If(self._byte_num < 4):
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# if bytes aren't valid ASCII then return to IDLE state
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with m.If(self._is_ascii_hex == 0):
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m.d.sync += self._state.eq(States.IDLE)
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# otherwise buffer them
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with m.Else():
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m.d.sync += self._buffer[self._byte_num].eq(
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self._from_ascii_hex
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)
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m.d.sync += self._byte_num.eq(self._byte_num + 1)
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with m.Else():
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m.d.sync += self._state.eq(States.IDLE)
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with m.If(self._state == States.WRITE):
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# buffer bytes if we don't have enough
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with m.If(self._byte_num < 8):
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# if bytes aren't valid ASCII then return to IDLE state
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with m.If(self._is_ascii_hex == 0):
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m.d.sync += self._state.eq(States.IDLE)
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# otherwise buffer them
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with m.Else():
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m.d.sync += self._buffer[self._byte_num].eq(
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self._from_ascii_hex
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)
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m.d.sync += self._byte_num.eq(self._byte_num + 1)
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with m.Else():
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m.d.sync += self._state.eq(States.IDLE)
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pass
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def elaborate(self, platform):
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m = Module()
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self._drive_ascii_signals(m)
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self._drive_output_bus(m)
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self._drive_fsm(m)
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return m
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@ -1,92 +0,0 @@
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from amaranth import *
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class TransmitBridge(Elaboratable):
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"""
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A module for bridging Manta's internal bus to the stream of bytes expected
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by the UARTTransmitter module.
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"""
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def __init__(self):
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# Top-Level Ports
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self.data_i = Signal(16)
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self.rw_i = Signal()
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self.valid_i = Signal()
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self.data_o = Signal(8)
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self.start_o = Signal()
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self.done_i = Signal()
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# Internal Signals
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self._buffer = Signal(16)
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self._count = Signal(4)
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self._busy = Signal()
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self._to_ascii_hex = Signal(8)
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self._n = Signal(4)
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def elaborate(self, platform):
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m = Module()
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m.d.comb += self.start_o.eq(self._busy)
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with m.If(~self._busy):
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with m.If((self.valid_i) & (~self.rw_i)):
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m.d.sync += self._busy.eq(1)
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m.d.sync += self._buffer.eq(self.data_i)
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with m.Else():
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# uart_tx is transmitting a byte:
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with m.If(self.done_i):
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m.d.sync += self._count.eq(self._count + 1)
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# Message has been transmitted
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with m.If(self._count > 5):
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m.d.sync += self._count.eq(0)
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# Go back to idle, or transmit next message
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with m.If((self.valid_i) & (~self.rw_i)):
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m.d.sync += self._buffer.eq(self.data_i)
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with m.Else():
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m.d.sync += self._busy.eq(0)
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# define to_ascii_hex
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with m.If(self._n < 10):
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m.d.comb += self._to_ascii_hex.eq(self._n + 0x30)
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with m.Else():
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m.d.comb += self._to_ascii_hex.eq(self._n + 0x41 - 10)
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# run the sequence
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with m.If(self._count == 0):
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m.d.comb += self._n.eq(0)
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m.d.comb += self.data_o.eq(ord("D"))
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with m.Elif(self._count == 1):
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m.d.comb += self._n.eq(self._buffer[12:16])
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m.d.comb += self.data_o.eq(self._to_ascii_hex)
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with m.Elif(self._count == 2):
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m.d.comb += self._n.eq(self._buffer[8:12])
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m.d.comb += self.data_o.eq(self._to_ascii_hex)
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with m.Elif(self._count == 3):
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m.d.comb += self._n.eq(self._buffer[4:8])
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m.d.comb += self.data_o.eq(self._to_ascii_hex)
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with m.Elif(self._count == 4):
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m.d.comb += self._n.eq(self._buffer[0:4])
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m.d.comb += self.data_o.eq(self._to_ascii_hex)
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with m.Elif(self._count == 5):
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m.d.comb += self._n.eq(0)
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m.d.comb += self.data_o.eq(ord("\r"))
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with m.Elif(self._count == 6):
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m.d.comb += self._n.eq(0)
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m.d.comb += self.data_o.eq(ord("\n"))
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with m.Else():
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m.d.comb += self._n.eq(0)
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m.d.comb += self.data_o.eq(0)
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return m
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