From 67dbac4a8140a1be949b2ab4b3146efa832cc001 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Wed, 11 Feb 2026 13:52:33 -0700 Subject: [PATCH] uart: remove unused receive and transmit bridges --- src/manta/uart/receive_bridge.py | 139 ------------------------------ src/manta/uart/transmit_bridge.py | 92 -------------------- 2 files changed, 231 deletions(-) delete mode 100644 src/manta/uart/receive_bridge.py delete mode 100644 src/manta/uart/transmit_bridge.py diff --git a/src/manta/uart/receive_bridge.py b/src/manta/uart/receive_bridge.py deleted file mode 100644 index c15c9f5..0000000 --- a/src/manta/uart/receive_bridge.py +++ /dev/null @@ -1,139 +0,0 @@ -from amaranth import * -from amaranth.lib.data import ArrayLayout -from amaranth.lib.enum import IntEnum - - -class States(IntEnum): - IDLE = 0 - READ = 1 - WRITE = 2 - - -class ReceiveBridge(Elaboratable): - """ - A module for bridging the stream of bytes from the UARTReceiver module to - Manta's internal bus. - """ - - def __init__(self): - # Top-Level Ports - self.data_i = Signal(8) - self.valid_i = Signal() - - self.addr_o = Signal(16) - self.data_o = Signal(16) - self.rw_o = Signal() - self.valid_o = Signal() - - # Internal Signals - self._buffer = Signal(ArrayLayout(4, 8)) - self._state = Signal(States) - self._byte_num = Signal(4) - self._is_eol = Signal() - self._is_ascii_hex = Signal() - self._from_ascii_hex = Signal(8) - - def _drive_ascii_signals(self, m): - # Decode 0-9 - with m.If((self.data_i >= 0x30) & (self.data_i <= 0x39)): - m.d.comb += self._is_ascii_hex.eq(1) - m.d.comb += self._from_ascii_hex.eq(self.data_i - 0x30) - - # Decode A-F - with m.Elif((self.data_i >= 0x41) & (self.data_i <= 0x46)): - m.d.comb += self._is_ascii_hex.eq(1) - m.d.comb += self._from_ascii_hex.eq(self.data_i - 0x41 + 10) - - with m.Else(): - m.d.comb += self._is_ascii_hex.eq(0) - m.d.comb += self._from_ascii_hex.eq(0) - - with m.If((self.data_i == ord("\r")) | (self.data_i == ord("\n"))): - m.d.comb += self._is_eol.eq(1) - - with m.Else(): - m.d.comb += self._is_eol.eq(0) - - def _drive_output_bus(self, m): - with m.If( - (self._state == States.READ) & (self._byte_num == 4) & (self._is_eol) - ): - m.d.comb += self.addr_o.eq( - Cat(self._buffer[3], self._buffer[2], self._buffer[1], self._buffer[0]) - ) - m.d.comb += self.data_o.eq(0) - m.d.comb += self.valid_o.eq(1) - m.d.comb += self.rw_o.eq(0) - - with m.Elif( - (self._state == States.WRITE) & (self._byte_num == 8) & (self._is_eol) - ): - m.d.comb += self.addr_o.eq( - Cat(self._buffer[3], self._buffer[2], self._buffer[1], self._buffer[0]) - ) - m.d.comb += self.data_o.eq( - Cat(self._buffer[7], self._buffer[6], self._buffer[5], self._buffer[4]) - ) - m.d.comb += self.valid_o.eq(1) - m.d.comb += self.rw_o.eq(1) - - with m.Else(): - m.d.comb += self.addr_o.eq(0) - m.d.comb += self.data_o.eq(0) - m.d.comb += self.rw_o.eq(0) - m.d.comb += self.valid_o.eq(0) - - def _drive_fsm(self, m): - with m.If(self.valid_i): - with m.If(self._state == States.IDLE): - m.d.sync += self._byte_num.eq(0) - - with m.If(self.data_i == ord("R")): - m.d.sync += self._state.eq(States.READ) - - with m.Elif(self.data_i == ord("W")): - m.d.sync += self._state.eq(States.WRITE) - - with m.If(self._state == States.READ): - # buffer bytes if we don't have enough - with m.If(self._byte_num < 4): - # if bytes aren't valid ASCII then return to IDLE state - with m.If(self._is_ascii_hex == 0): - m.d.sync += self._state.eq(States.IDLE) - - # otherwise buffer them - with m.Else(): - m.d.sync += self._buffer[self._byte_num].eq( - self._from_ascii_hex - ) - m.d.sync += self._byte_num.eq(self._byte_num + 1) - - with m.Else(): - m.d.sync += self._state.eq(States.IDLE) - - with m.If(self._state == States.WRITE): - # buffer bytes if we don't have enough - with m.If(self._byte_num < 8): - # if bytes aren't valid ASCII then return to IDLE state - with m.If(self._is_ascii_hex == 0): - m.d.sync += self._state.eq(States.IDLE) - - # otherwise buffer them - with m.Else(): - m.d.sync += self._buffer[self._byte_num].eq( - self._from_ascii_hex - ) - m.d.sync += self._byte_num.eq(self._byte_num + 1) - - with m.Else(): - m.d.sync += self._state.eq(States.IDLE) - pass - - def elaborate(self, platform): - m = Module() - - self._drive_ascii_signals(m) - self._drive_output_bus(m) - self._drive_fsm(m) - - return m diff --git a/src/manta/uart/transmit_bridge.py b/src/manta/uart/transmit_bridge.py deleted file mode 100644 index f7f51c4..0000000 --- a/src/manta/uart/transmit_bridge.py +++ /dev/null @@ -1,92 +0,0 @@ -from amaranth import * - - -class TransmitBridge(Elaboratable): - """ - A module for bridging Manta's internal bus to the stream of bytes expected - by the UARTTransmitter module. - """ - - def __init__(self): - # Top-Level Ports - self.data_i = Signal(16) - self.rw_i = Signal() - self.valid_i = Signal() - - self.data_o = Signal(8) - self.start_o = Signal() - self.done_i = Signal() - - # Internal Signals - self._buffer = Signal(16) - self._count = Signal(4) - self._busy = Signal() - self._to_ascii_hex = Signal(8) - self._n = Signal(4) - - def elaborate(self, platform): - m = Module() - - m.d.comb += self.start_o.eq(self._busy) - - with m.If(~self._busy): - with m.If((self.valid_i) & (~self.rw_i)): - m.d.sync += self._busy.eq(1) - m.d.sync += self._buffer.eq(self.data_i) - - with m.Else(): - # uart_tx is transmitting a byte: - with m.If(self.done_i): - m.d.sync += self._count.eq(self._count + 1) - - # Message has been transmitted - with m.If(self._count > 5): - m.d.sync += self._count.eq(0) - - # Go back to idle, or transmit next message - with m.If((self.valid_i) & (~self.rw_i)): - m.d.sync += self._buffer.eq(self.data_i) - - with m.Else(): - m.d.sync += self._busy.eq(0) - - # define to_ascii_hex - with m.If(self._n < 10): - m.d.comb += self._to_ascii_hex.eq(self._n + 0x30) - with m.Else(): - m.d.comb += self._to_ascii_hex.eq(self._n + 0x41 - 10) - - # run the sequence - with m.If(self._count == 0): - m.d.comb += self._n.eq(0) - m.d.comb += self.data_o.eq(ord("D")) - - with m.Elif(self._count == 1): - m.d.comb += self._n.eq(self._buffer[12:16]) - m.d.comb += self.data_o.eq(self._to_ascii_hex) - - with m.Elif(self._count == 2): - m.d.comb += self._n.eq(self._buffer[8:12]) - m.d.comb += self.data_o.eq(self._to_ascii_hex) - - with m.Elif(self._count == 3): - m.d.comb += self._n.eq(self._buffer[4:8]) - m.d.comb += self.data_o.eq(self._to_ascii_hex) - - with m.Elif(self._count == 4): - m.d.comb += self._n.eq(self._buffer[0:4]) - m.d.comb += self.data_o.eq(self._to_ascii_hex) - - with m.Elif(self._count == 5): - m.d.comb += self._n.eq(0) - m.d.comb += self.data_o.eq(ord("\r")) - - with m.Elif(self._count == 6): - m.d.comb += self._n.eq(0) - m.d.comb += self.data_o.eq(ord("\n")) - - with m.Else(): - m.d.comb += self._n.eq(0) - m.d.comb += self.data_o.eq(0) - - return m