blacken code
This commit is contained in:
Fischer Moseley
parent
e48f60e03a
commit
030a841f53
4
build.py
4
build.py
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@ -1,5 +1,5 @@
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import os
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os.system('echo "#!/usr/bin/python3" > manta')
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os.system('cat manta.py >> manta')
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os.system('chmod +x manta')
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os.system("cat manta.py >> manta")
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os.system("chmod +x manta")
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253
manta.py
253
manta.py
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@ -7,136 +7,164 @@ import serial
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debug = True
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version = '0.0.0'
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version = "0.0.0"
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def load_source_files(path):
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"""concatenates the list of files provided into a single string"""
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source_files = [f for f in os.listdir(path) if os.path.isfile(os.path.join(path, f))]
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source_files = [f for f in source_files if f.split('.')[-1] in ['sv', 'v']]
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source_files = [
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f for f in os.listdir(path) if os.path.isfile(os.path.join(path, f))
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]
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source_files = [f for f in source_files if f.split(".")[-1] in ["sv", "v"]]
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buf = ""
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for source_file in source_files:
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with open(path + source_file, 'r') as f:
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with open(path + source_file, "r") as f:
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buf += f.read()
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return buf
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downlink_template = load_source_files('src/')
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downlink_template = load_source_files("src/")
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def load_config(path):
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"""Take path to configuration file, and retun the configuration as a python list/dict object."""
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extension = path.split('.')[-1]
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extension = path.split(".")[-1]
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if 'json' in extension:
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with open(path, 'r') as f:
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if "json" in extension:
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with open(path, "r") as f:
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config = json.load(f)
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return config
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elif 'yaml' in extension or 'yml' in extension:
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with open(path, 'r') as f:
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elif "yaml" in extension or "yml" in extension:
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with open(path, "r") as f:
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config = yaml.safe_load(f)
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return config
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else:
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raise ValueError('Unable to recognize configuration file extension.')
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raise ValueError("Unable to recognize configuration file extension.")
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def check_config(config):
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"""Takes a list/dict python object representing a core configuration and throws an error if it is misconfigured."""
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assert 'downlink' in config or 'uplink' in config, 'No downlink or uplink specified.'
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assert (
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"downlink" in config or "uplink" in config
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), "No downlink or uplink specified."
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if 'downlink' in config:
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dl = config['downlink']
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assert dl['sample_depth'], 'Downlink core specified, but sample_depth not specified.'
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assert dl['clock_freq'], 'Downlink core specified, but clock_freq not specified.'
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assert dl['probes'] and len(dl['probes']) > 0, 'Downlink core specified, but no probes specified.'
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assert dl['triggers'] and len(dl['triggers']) > 0, 'Downlink core specified, but no triggers specified.'
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if "downlink" in config:
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dl = config["downlink"]
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assert dl[
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"sample_depth"
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], "Downlink core specified, but sample_depth not specified."
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assert dl[
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"clock_freq"
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], "Downlink core specified, but clock_freq not specified."
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assert (
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dl["probes"] and len(dl["probes"]) > 0
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), "Downlink core specified, but no probes specified."
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assert (
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dl["triggers"] and len(dl["triggers"]) > 0
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), "Downlink core specified, but no triggers specified."
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# confirm core clock is sufficiently fast
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prescaler = dl['clock_freq'] // config['uart']['baudrate']
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prescaler = dl["clock_freq"] // config["uart"]["baudrate"]
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assert prescaler >= 2
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# confirm actual baudrate and target baudrate are within 5%
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actual_baudrate = config['downlink']['clock_freq'] / prescaler
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baudrate_error = abs(actual_baudrate - config['uart']['baudrate']) / config['uart']['baudrate']
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assert baudrate_error <= 0.05, f'Unable to match target baudrate! Actual baudrate differs from target by {round(100*baudrate_error, 2)}%'
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actual_baudrate = config["downlink"]["clock_freq"] / prescaler
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baudrate_error = (
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abs(actual_baudrate - config["uart"]["baudrate"])
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/ config["uart"]["baudrate"]
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)
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assert (
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baudrate_error <= 0.05
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), f"Unable to match target baudrate! Actual baudrate differs from target by {round(100*baudrate_error, 2)}%"
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if debug:
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print(f'UART interface on debug core will the following configuration:')
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print(f"UART interface on debug core will the following configuration:")
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print(f' - target_baudrate: {config["uart"]["baudrate"]}')
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print(f' - prescaler: {prescaler}')
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print(f' - actual_baudrate: {round(actual_baudrate, 2)}')
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print(f" - prescaler: {prescaler}")
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print(f" - actual_baudrate: {round(actual_baudrate, 2)}")
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if 'uplink' in config:
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raise NotImplementedError('Cannot check configuration validity for uplinks just yet!')
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if "uplink" in config:
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raise NotImplementedError(
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"Cannot check configuration validity for uplinks just yet!"
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)
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if 'uart' in config:
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uart = config['uart']
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if "uart" in config:
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uart = config["uart"]
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# confirm number of data bits is valid
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assert 'data' in uart, 'Number of data bits in UART interface not specified.'
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assert uart['data'] in [8, 7, 6, 5], 'Invalid number of data bits.'
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assert "data" in uart, "Number of data bits in UART interface not specified."
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assert uart["data"] in [8, 7, 6, 5], "Invalid number of data bits."
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# confirm number of stop bits is valid
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assert uart['stop'] in [1, 1.5, 2], 'Invalid number of stop bits.'
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assert uart["stop"] in [1, 1.5, 2], "Invalid number of stop bits."
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# confirm parity is valid
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assert uart['parity'] in ['none', 'even', 'odd', 'mark', 'space'], 'Invalid parity setting.'
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assert uart["parity"] in [
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"none",
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"even",
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"odd",
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"mark",
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"space",
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], "Invalid parity setting."
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def gen_downlink_core(config):
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buf = downlink_template
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dl = config['downlink']
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dl = config["downlink"]
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# add timestamp
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timestamp = datetime.now().strftime("%d/%m/%Y %H:%M:%S")
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buf = buf.replace('@TIMESTAMP', timestamp)
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buf = buf.replace("@TIMESTAMP", timestamp)
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# add user
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user = os.environ.get('USER', os.environ.get('USERNAME'))
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buf = buf.replace('@USER', user)
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user = os.environ.get("USER", os.environ.get("USERNAME"))
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buf = buf.replace("@USER", user)
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# add trigger
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trigger = [f'({trigger})' for trigger in dl['triggers']]
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trigger = ' || '.join(trigger)
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buf = buf.replace('@TRIGGER', trigger)
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trigger = [f"({trigger})" for trigger in dl["triggers"]]
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trigger = " || ".join(trigger)
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buf = buf.replace("@TRIGGER", trigger)
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# add concat
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concat = [name for name in dl['probes']]
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concat = ', '.join(concat)
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concat = '{' + concat + '};'
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buf = buf.replace('@CONCAT', concat)
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concat = [name for name in dl["probes"]]
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concat = ", ".join(concat)
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concat = "{" + concat + "};"
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buf = buf.replace("@CONCAT", concat)
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# add probes
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probe_verilog = []
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for name, width in dl['probes'].items():
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for name, width in dl["probes"].items():
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if width == 1:
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probe_verilog.append(f'input wire {name},')
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probe_verilog.append(f"input wire {name},")
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else:
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probe_verilog.append(f'input wire [{width-1}:0] {name},')
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probe_verilog.append(f"input wire [{width-1}:0] {name},")
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probe_verilog = '\n\t'.join(probe_verilog)
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buf = buf.replace('@PROBES', probe_verilog)
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probe_verilog = "\n\t".join(probe_verilog)
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buf = buf.replace("@PROBES", probe_verilog)
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# add sample width
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sample_width = sum([width for name, width in dl['probes'].items()])
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buf = buf.replace('@SAMPLE_WIDTH', str(sample_width))
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sample_width = sum([width for name, width in dl["probes"].items()])
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buf = buf.replace("@SAMPLE_WIDTH", str(sample_width))
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# add sample depth
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buf = buf.replace('@SAMPLE_DEPTH', str(dl['sample_depth']))
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buf = buf.replace("@SAMPLE_DEPTH", str(dl["sample_depth"]))
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# uart config
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buf = buf.replace('@DATA_WIDTH', str(config['uart']['data']))
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buf = buf.replace('@BAUDRATE', str(config['uart']['baudrate']))
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buf = buf.replace('@CLK_FREQ_HZ', str(dl['clock_freq']))
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buf = buf.replace("@DATA_WIDTH", str(config["uart"]["data"]))
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buf = buf.replace("@BAUDRATE", str(config["uart"]["baudrate"]))
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buf = buf.replace("@CLK_FREQ_HZ", str(dl["clock_freq"]))
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return buf
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def print_help():
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help = f"""
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Manta v{version} - An In-Situ Debugging Tool for Programmable Hardware
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@ -151,6 +179,7 @@ Supported commands:
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"""
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print(help)
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def print_ray():
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color_ray = f"""
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\033[96m (\.-./)
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@ -168,110 +197,117 @@ def print_ray():
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\033[96m '-....-' \033[00m"""
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print(color_ray)
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def setup_serial(ser, config):
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ser.baudrate = config['uart']['baudrate']
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ser.port = config['uart']['port']
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ser.timeout = config['uart']['timeout']
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ser.baudrate = config["uart"]["baudrate"]
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ser.port = config["uart"]["port"]
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ser.timeout = config["uart"]["timeout"]
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# setup number of data bits
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if config['uart']['data'] == 8:
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if config["uart"]["data"] == 8:
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ser.bytesize = serial.EIGHTBITS
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elif config['uart']['data'] == 7:
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elif config["uart"]["data"] == 7:
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ser.bytesize = serial.SEVENBITS
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elif config['uart']['data'] == 6:
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elif config["uart"]["data"] == 6:
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ser.bytesize = serial.SIXBITS
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elif config['uart']['data'] == 5:
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elif config["uart"]["data"] == 5:
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ser.bytesize = serial.FIVEBITS
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else:
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raise ValueError("Invalid number of data bits in UART configuration.")
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# setup number of stop bits
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if config['uart']['stop'] == 1:
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if config["uart"]["stop"] == 1:
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ser.stopbits = serial.STOPBITS_ONE
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elif config['uart']['stop'] == 1.5:
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elif config["uart"]["stop"] == 1.5:
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ser.stopbits = serial.STOPBITS_ONE_POINT_FIVE
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elif config['uart']['stop'] == 2:
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elif config["uart"]["stop"] == 2:
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ser.stopbits = serial.STOPBITS_TWO
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else:
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raise ValueError("Invalid number of stop bits in UART configuration.")
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# setup parity
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if config['uart']['parity'] == 'none':
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if config["uart"]["parity"] == "none":
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ser.parity = serial.PARITY_NONE
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elif config['uart']['parity'] == 'even':
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elif config["uart"]["parity"] == "even":
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ser.parity = serial.PARITY_EVEN
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elif config['uart']['parity'] == 'odd':
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elif config["uart"]["parity"] == "odd":
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ser.parity = serial.PARITY_ODD
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elif config['uart']['parity'] == 'mark':
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elif config["uart"]["parity"] == "mark":
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ser.parity = serial.PARITY_MARK
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elif config['uart']['parity'] == 'space':
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elif config["uart"]["parity"] == "space":
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ser.parity = serial.PARITY_SPACE
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else:
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raise ValueError("Invalid parity setting in UART configuration.")
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def read_serial(config):
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# obtain bytestream from FPGA
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with serial.Serial() as ser:
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setup_serial(ser, config)
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ser.open()
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ser.flushInput()
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ser.write(b'\x30')
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ser.write(b"\x30")
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data = ser.read(4096)
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return data
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def part_select(data, width):
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top, bottom = width
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assert top >= bottom
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mask = 2**(top - bottom + 1) - 1
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mask = 2 ** (top - bottom + 1) - 1
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return (data >> bottom) & mask
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def make_widths(config):
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# {probe0, probe1, probe2}
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# [12, 1, 3] should produce
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# [ (11,0) , (12, 12), (15,13) ]
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# {probe0, probe1, probe2}
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# [12, 1, 3] should produce
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# [ (11,0) , (12, 12), (15,13) ]
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widths = list(config['probes'].values())
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widths = list(config["probes"].values())
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parts = []
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for i, width in enumerate(widths):
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if (i == 0):
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parts.append( (width - 1, 0) )
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parts = []
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for i, width in enumerate(widths):
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if i == 0:
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parts.append((width - 1, 0))
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else:
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parts.append( ((parts[i-1][1] + width) , (parts[i-1][1] + 1)) )
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else:
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parts.append(((parts[i - 1][1] + width), (parts[i - 1][1] + 1)))
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# reversing this list is a little bit of a hack, should fix/document
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return parts[::-1]
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# reversing this list is a little bit of a hack, should fix/document
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return parts[::-1]
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def export_waveform(config, data, path):
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extension = path.split('.')[-1]
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extension = path.split(".")[-1]
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if extension == 'vcd':
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if extension == "vcd":
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from vcd import VCDWriter
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vcd_file = open(path, 'w')
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vcd_file = open(path, "w")
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timestamp = datetime.now().strftime("%d/%m/%Y %H:%M:%S")
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with VCDWriter(vcd_file, timescale='10 ns', date=timestamp, version = 'manta') as writer:
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with VCDWriter(
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vcd_file, timescale="10 ns", date=timestamp, version="manta"
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) as writer:
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# add probes to vcd file
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vcd_probes = []
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for name, width in config['probes'].items():
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probe = writer.register_var('ila', name, 'wire', size = width)
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for name, width in config["probes"].items():
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probe = writer.register_var("ila", name, "wire", size=width)
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vcd_probes.append(probe)
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# calculate bit widths for part selecting
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@ -286,48 +322,53 @@ def export_waveform(config, data, path):
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vcd_file.close()
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else:
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raise NotImplementedError('More file formats to come!')
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raise NotImplementedError("More file formats to come!")
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if __name__ == '__main__':
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if __name__ == "__main__":
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# print help menu if no args passed or help menu requested
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if len(argv) == 1 or argv[1] == 'help':
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if len(argv) == 1 or argv[1] == "help":
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print_help()
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exit()
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# open minicom-like serial terminal with given config
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elif argv[1] == 'terminal':
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assert len(argv) == 3, 'Not enough (or too many) config files specified.'
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elif argv[1] == "terminal":
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assert len(argv) == 3, "Not enough (or too many) config files specified."
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# TODO: make this work with a looser config file - it should work even if we just have a uart definition
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config = load_config(argv[2])
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check_config(config)
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raise NotImplementedError('Miniterm console is still under development!')
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raise NotImplementedError("Miniterm console is still under development!")
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# list available serial ports
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elif argv[1] == 'ports':
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elif argv[1] == "ports":
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import serial.tools.list_ports
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for info in serial.tools.list_ports.comports():
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print(info)
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# show splash screen
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elif argv[1] == 'ray':
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elif argv[1] == "ray":
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print_ray()
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exit()
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# generate the specified core
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elif argv[1] == 'gen':
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assert len(argv) == 4, 'Wrong number of arguments, only a config file and output file must both be specified.'
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elif argv[1] == "gen":
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assert (
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len(argv) == 4
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), "Wrong number of arguments, only a config file and output file must both be specified."
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config = load_config(argv[2])
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check_config(config)
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with open(argv[3], 'w') as f:
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with open(argv[3], "w") as f:
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f.write(gen_downlink_core(config))
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# run the specified core
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elif argv[1] == 'run':
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assert len(argv) == 4, 'Wrong number of arguments, only a config file and output file must both be specified.'
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elif argv[1] == "run":
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assert (
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len(argv) == 4
|
||||
), "Wrong number of arguments, only a config file and output file must both be specified."
|
||||
config = load_config(argv[2])
|
||||
check_config(config)
|
||||
|
||||
|
|
@ -335,5 +376,5 @@ if __name__ == '__main__':
|
|||
export_waveform(config, data, argv[3])
|
||||
|
||||
else:
|
||||
print('Option not recognized.')
|
||||
print("Option not recognized.")
|
||||
print_help()
|
||||
|
|
|
|||
Loading…
Reference in New Issue