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Fischer Moseley 2023-02-04 12:45:52 -05:00
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![](assets/manta.png)
![Functional Simulation](https://github.com/fischermoseley/manta/actions/workflows/run_all_tests.yml/badge.svg)
![Formal Verification](https://github.com/fischermoseley/manta/actions/workflows/run_all_tests.yml/badge.svg)
Manta is a tool for debugging FPGA designs over UART. It has two modes for doing this, downlink and uplink. The downlink mode feels similar to a logic analyzer, in that Manta provides a waveform view of a configurable set of signals, which get captured when some trigger condition is met. The uplink mode allows a host machine to remotely set values of registers on the FPGA via a python interface. This permits rapid prototyping of logic in Python, and a means of incrementally migrating it to HDL. A more detailed description of each mode is below.
Manta is written in Python, and generates SystemVerilog HDL. It's cross-platform, and its only dependency is pySerial. The SystemVerilog templates are included in the Python source, so only a single python file must be included in your project.