From 514179fc0ae2ca1e83641b8aa6b7c0e8c2243b9b Mon Sep 17 00:00:00 2001 From: Fischer Moseley Date: Sat, 4 Feb 2023 12:45:52 -0500 Subject: [PATCH] add test badge --- README.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/README.md b/README.md index 02788b7..f9b8f16 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,8 @@ ![](assets/manta.png) +![Functional Simulation](https://github.com/fischermoseley/manta/actions/workflows/run_all_tests.yml/badge.svg) +![Formal Verification](https://github.com/fischermoseley/manta/actions/workflows/run_all_tests.yml/badge.svg) + Manta is a tool for debugging FPGA designs over UART. It has two modes for doing this, downlink and uplink. The downlink mode feels similar to a logic analyzer, in that Manta provides a waveform view of a configurable set of signals, which get captured when some trigger condition is met. The uplink mode allows a host machine to remotely set values of registers on the FPGA via a python interface. This permits rapid prototyping of logic in Python, and a means of incrementally migrating it to HDL. A more detailed description of each mode is below. Manta is written in Python, and generates SystemVerilog HDL. It's cross-platform, and its only dependency is pySerial. The SystemVerilog templates are included in the Python source, so only a single python file must be included in your project.