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logic_analyzer: pass interface when constructing LogicAnalyzerCapture

This commit is contained in:
Fischer Moseley 2024-10-07 23:14:29 -07:00
parent 583d9e0d83
commit 4b7c03e722
2 changed files with 7 additions and 2 deletions
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6
src/manta/logic_analyzer/__init__.py
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@ -317,5 +317,9 @@ class LogicAnalyzerCore(MantaCore):
data = raw_capture[read_pointer:] + raw_capture[:read_pointer] data = raw_capture[read_pointer:] + raw_capture[:read_pointer]
return LogicAnalyzerCapture( return LogicAnalyzerCapture(
self._probes, self._trigger_location, self._trigger_mode, data self._probes,
self._trigger_location,
self._trigger_mode,
data,
self.interface,
) )

3
src/manta/logic_analyzer/capture.py
View File

@ -14,11 +14,12 @@ class LogicAnalyzerCapture:
CSV file, or a Verilog module. CSV file, or a Verilog module.
""" """
def __init__(self, probes, trigger_location, trigger_mode, data): def __init__(self, probes, trigger_location, trigger_mode, data, interface):
self._probes = probes self._probes = probes
self._trigger_location = trigger_location self._trigger_location = trigger_location
self._trigger_mode = trigger_mode self._trigger_mode = trigger_mode
self._data = data self._data = data
self._interface = interface
def get_trigger_location(self): def get_trigger_location(self):
""" """