diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py
index b566421..0c5f380 100644
--- a/src/manta/logic_analyzer/__init__.py
+++ b/src/manta/logic_analyzer/__init__.py
@@ -317,5 +317,9 @@ class LogicAnalyzerCore(MantaCore):
 
         data = raw_capture[read_pointer:] + raw_capture[:read_pointer]
         return LogicAnalyzerCapture(
-            self._probes, self._trigger_location, self._trigger_mode, data
+            self._probes,
+            self._trigger_location,
+            self._trigger_mode,
+            data,
+            self.interface,
         )
diff --git a/src/manta/logic_analyzer/capture.py b/src/manta/logic_analyzer/capture.py
index 5a5e2eb..731f654 100644
--- a/src/manta/logic_analyzer/capture.py
+++ b/src/manta/logic_analyzer/capture.py
@@ -14,11 +14,12 @@ class LogicAnalyzerCapture:
     CSV file, or a Verilog module.
     """
 
-    def __init__(self, probes, trigger_location, trigger_mode, data):
+    def __init__(self, probes, trigger_location, trigger_mode, data, interface):
         self._probes = probes
         self._trigger_location = trigger_location
         self._trigger_mode = trigger_mode
         self._data = data
+        self._interface = interface
 
     def get_trigger_location(self):
         """