uart: remove unused bridge testbenches
This commit is contained in:
Fischer Moseley
parent
45ca46bf02
commit
498de60ff2
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@ -1,113 +0,0 @@
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from manta.uart import ReceiveBridge
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from manta.utils import *
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bridge_rx = ReceiveBridge()
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async def verify_read_decoding(ctx, bytes, addr):
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"""
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Send a series of bytes to the receive bridge, and verify that the bridge places
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a read request with the appropriate address on the internal bus.
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"""
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valid_asserted = False
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ctx.set(bridge_rx.valid_i, True)
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for i, byte in enumerate(bytes):
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ctx.set(bridge_rx.data_i, byte)
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if ctx.get(bridge_rx.valid_o) and (i > 0):
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valid_asserted = True
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if ctx.get(bridge_rx.addr_o) != addr:
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raise ValueError("wrong addr!")
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if ctx.get(bridge_rx.rw_o) != 0:
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raise ValueError("wrong rw!")
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if ctx.get(bridge_rx.data_o) != 0:
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raise ValueError("wrong data!")
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await ctx.tick()
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ctx.set(bridge_rx.valid_i, False)
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ctx.set(bridge_rx.data_i, 0)
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if not valid_asserted and not ctx.get(bridge_rx.valid_o):
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raise ValueError("Bridge failed to output valid message.")
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async def verify_write_decoding(ctx, bytes, addr, data):
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"""
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Send a series of bytes to the receive bridge, and verify that the bridge places
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a write request with the appropriate address and data on the internal bus.
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"""
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valid_asserted = False
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ctx.set(bridge_rx.valid_i, True)
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for i, byte in enumerate(bytes):
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ctx.set(bridge_rx.data_i, byte)
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if ctx.get(bridge_rx.valid_o) and (i > 0):
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valid_asserted = True
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if ctx.get(bridge_rx.addr_o) != addr:
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raise ValueError("wrong addr!")
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if ctx.get(bridge_rx.rw_o) != 1:
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raise ValueError("wrong rw!")
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if ctx.get(bridge_rx.data_o) != data:
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raise ValueError("wrong data!")
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await ctx.tick()
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ctx.set(bridge_rx.valid_i, False)
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ctx.set(bridge_rx.data_i, 0)
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if not valid_asserted and not ctx.get(bridge_rx.valid_o):
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raise ValueError("Bridge failed to output valid message.")
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async def verify_bad_bytes(ctx, bytes):
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"""
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Send a series of bytes to the receive bridge, and verify that the bridge does not
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place any transaction on the internal bus.
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"""
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ctx.set(bridge_rx.valid_i, True)
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for byte in bytes:
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ctx.set(bridge_rx.data_i, byte)
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if ctx.get(bridge_rx.valid_o):
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raise ValueError("Bridge decoded invalid message.")
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await ctx.tick()
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ctx.set(bridge_rx.valid_i, 0)
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@simulate(bridge_rx)
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async def test_function(ctx):
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await verify_read_decoding(ctx, b"R0000\r\n", 0x0000)
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await verify_read_decoding(ctx, b"R1234\r\n", 0x1234)
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await verify_read_decoding(ctx, b"RBABE\r\n", 0xBABE)
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await verify_read_decoding(ctx, b"R5678\n", 0x5678)
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await verify_read_decoding(ctx, b"R9ABC\r", 0x9ABC)
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@simulate(bridge_rx)
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async def test_write_decode(ctx):
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await verify_write_decoding(ctx, b"W12345678\r\n", 0x1234, 0x5678)
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await verify_write_decoding(ctx, b"WDEADBEEF\r\n", 0xDEAD, 0xBEEF)
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await verify_write_decoding(ctx, b"WDEADBEEF\r", 0xDEAD, 0xBEEF)
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await verify_write_decoding(ctx, b"WB0BACAFE\n", 0xB0BA, 0xCAFE)
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@simulate(bridge_rx)
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async def test_no_decode(ctx):
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await verify_bad_bytes(ctx, b"RABC\r\n")
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await verify_bad_bytes(ctx, b"R12345\r\n")
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await verify_bad_bytes(ctx, b"M\r\n")
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await verify_bad_bytes(ctx, b"W123456789101112131415161718191201222\r\n")
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await verify_bad_bytes(ctx, b"RABCG\r\n")
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await verify_bad_bytes(ctx, b"WABC[]()##*@\r\n")
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await verify_bad_bytes(ctx, b"R\r\n")
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@ -1,60 +0,0 @@
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from random import sample
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from manta.uart import TransmitBridge
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from manta.utils import *
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bridge_tx = TransmitBridge()
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async def verify_encoding(ctx, data, bytes):
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"""
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Place a read response on the internal bus, and verify that the sequence of bytes
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sent from TransmitBridge matches the provided bytestring `bytes`.
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This function also models an ideal UARTTransmitter module, which begins transmitting
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bytes when `start` is asserted, and reports when it is done by asserting `done`.
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"""
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# Place a read response on the internal bus
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ctx.set(bridge_tx.data_i, data)
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ctx.set(bridge_tx.valid_i, True)
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ctx.set(bridge_tx.rw_i, 0)
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ctx.set(bridge_tx.done_i, True)
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await ctx.tick()
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ctx.set(bridge_tx.data_i, 0)
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ctx.set(bridge_tx.valid_i, False)
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ctx.set(bridge_tx.rw_i, 0)
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# Model the UARTTransmitter
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sent_bytes = b""
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iters = 0
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while len(sent_bytes) < len(bytes):
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# If start_o is asserted, set done_i to zero, then delay, then set it back to one
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if ctx.get(bridge_tx.start_o):
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sent_bytes += ctx.get(bridge_tx.data_o).to_bytes(1, "big")
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ctx.set(bridge_tx.done_i, 0)
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for _ in range(10):
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await ctx.tick()
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ctx.set(bridge_tx.done_i, 1)
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await ctx.tick()
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# Time out if not enough bytes after trying to get bytes 15 times
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iters += 1
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if iters > 15:
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raise ValueError("Timed out waiting for bytes.")
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# Verify bytes sent from ReceiveBridge match expected_bytes
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if sent_bytes != bytes:
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raise ValueError(f"Received {sent_bytes} instead of {bytes}.")
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@simulate(bridge_tx)
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async def test_some_random_values(ctx):
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for i in sample(range(0xFFFF), k=5000):
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expected = f"D{i:04X}\r\n".encode("ascii")
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await verify_encoding(ctx, i, expected)
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