From 498de60ff2e72e0589ae36f4629d3ab6a15d39f8 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Wed, 11 Feb 2026 14:55:34 -0700 Subject: [PATCH] uart: remove unused bridge testbenches --- test/test_bridge_rx_sim.py | 113 ------------------------------------- test/test_bridge_tx_sim.py | 60 -------------------- 2 files changed, 173 deletions(-) delete mode 100644 test/test_bridge_rx_sim.py delete mode 100644 test/test_bridge_tx_sim.py diff --git a/test/test_bridge_rx_sim.py b/test/test_bridge_rx_sim.py deleted file mode 100644 index beb603e..0000000 --- a/test/test_bridge_rx_sim.py +++ /dev/null @@ -1,113 +0,0 @@ -from manta.uart import ReceiveBridge -from manta.utils import * - -bridge_rx = ReceiveBridge() - - -async def verify_read_decoding(ctx, bytes, addr): - """ - Send a series of bytes to the receive bridge, and verify that the bridge places - a read request with the appropriate address on the internal bus. - """ - - valid_asserted = False - ctx.set(bridge_rx.valid_i, True) - - for i, byte in enumerate(bytes): - ctx.set(bridge_rx.data_i, byte) - - if ctx.get(bridge_rx.valid_o) and (i > 0): - valid_asserted = True - if ctx.get(bridge_rx.addr_o) != addr: - raise ValueError("wrong addr!") - - if ctx.get(bridge_rx.rw_o) != 0: - raise ValueError("wrong rw!") - - if ctx.get(bridge_rx.data_o) != 0: - raise ValueError("wrong data!") - - await ctx.tick() - - ctx.set(bridge_rx.valid_i, False) - ctx.set(bridge_rx.data_i, 0) - - if not valid_asserted and not ctx.get(bridge_rx.valid_o): - raise ValueError("Bridge failed to output valid message.") - - -async def verify_write_decoding(ctx, bytes, addr, data): - """ - Send a series of bytes to the receive bridge, and verify that the bridge places - a write request with the appropriate address and data on the internal bus. - """ - valid_asserted = False - ctx.set(bridge_rx.valid_i, True) - - for i, byte in enumerate(bytes): - ctx.set(bridge_rx.data_i, byte) - - if ctx.get(bridge_rx.valid_o) and (i > 0): - valid_asserted = True - if ctx.get(bridge_rx.addr_o) != addr: - raise ValueError("wrong addr!") - - if ctx.get(bridge_rx.rw_o) != 1: - raise ValueError("wrong rw!") - - if ctx.get(bridge_rx.data_o) != data: - raise ValueError("wrong data!") - - await ctx.tick() - - ctx.set(bridge_rx.valid_i, False) - ctx.set(bridge_rx.data_i, 0) - - if not valid_asserted and not ctx.get(bridge_rx.valid_o): - raise ValueError("Bridge failed to output valid message.") - - -async def verify_bad_bytes(ctx, bytes): - """ - Send a series of bytes to the receive bridge, and verify that the bridge does not - place any transaction on the internal bus. - """ - ctx.set(bridge_rx.valid_i, True) - - for byte in bytes: - ctx.set(bridge_rx.data_i, byte) - - if ctx.get(bridge_rx.valid_o): - raise ValueError("Bridge decoded invalid message.") - - await ctx.tick() - - ctx.set(bridge_rx.valid_i, 0) - - -@simulate(bridge_rx) -async def test_function(ctx): - await verify_read_decoding(ctx, b"R0000\r\n", 0x0000) - await verify_read_decoding(ctx, b"R1234\r\n", 0x1234) - await verify_read_decoding(ctx, b"RBABE\r\n", 0xBABE) - await verify_read_decoding(ctx, b"R5678\n", 0x5678) - await verify_read_decoding(ctx, b"R9ABC\r", 0x9ABC) - - -@simulate(bridge_rx) -async def test_write_decode(ctx): - await verify_write_decoding(ctx, b"W12345678\r\n", 0x1234, 0x5678) - await verify_write_decoding(ctx, b"WDEADBEEF\r\n", 0xDEAD, 0xBEEF) - await verify_write_decoding(ctx, b"WDEADBEEF\r", 0xDEAD, 0xBEEF) - await verify_write_decoding(ctx, b"WB0BACAFE\n", 0xB0BA, 0xCAFE) - - -@simulate(bridge_rx) -async def test_no_decode(ctx): - await verify_bad_bytes(ctx, b"RABC\r\n") - await verify_bad_bytes(ctx, b"R12345\r\n") - await verify_bad_bytes(ctx, b"M\r\n") - await verify_bad_bytes(ctx, b"W123456789101112131415161718191201222\r\n") - await verify_bad_bytes(ctx, b"RABCG\r\n") - await verify_bad_bytes(ctx, b"WABC[]()##*@\r\n") - await verify_bad_bytes(ctx, b"R\r\n") diff --git a/test/test_bridge_tx_sim.py b/test/test_bridge_tx_sim.py deleted file mode 100644 index b9429d8..0000000 --- a/test/test_bridge_tx_sim.py +++ /dev/null @@ -1,60 +0,0 @@ -from random import sample - -from manta.uart import TransmitBridge -from manta.utils import * - -bridge_tx = TransmitBridge() - - -async def verify_encoding(ctx, data, bytes): - """ - Place a read response on the internal bus, and verify that the sequence of bytes - sent from TransmitBridge matches the provided bytestring `bytes`. - - This function also models an ideal UARTTransmitter module, which begins transmitting - bytes when `start` is asserted, and reports when it is done by asserting `done`. - """ - - # Place a read response on the internal bus - ctx.set(bridge_tx.data_i, data) - ctx.set(bridge_tx.valid_i, True) - ctx.set(bridge_tx.rw_i, 0) - ctx.set(bridge_tx.done_i, True) - - await ctx.tick() - - ctx.set(bridge_tx.data_i, 0) - ctx.set(bridge_tx.valid_i, False) - ctx.set(bridge_tx.rw_i, 0) - - # Model the UARTTransmitter - sent_bytes = b"" - iters = 0 - - while len(sent_bytes) < len(bytes): - # If start_o is asserted, set done_i to zero, then delay, then set it back to one - if ctx.get(bridge_tx.start_o): - sent_bytes += ctx.get(bridge_tx.data_o).to_bytes(1, "big") - ctx.set(bridge_tx.done_i, 0) - - for _ in range(10): - await ctx.tick() - - ctx.set(bridge_tx.done_i, 1) - await ctx.tick() - - # Time out if not enough bytes after trying to get bytes 15 times - iters += 1 - if iters > 15: - raise ValueError("Timed out waiting for bytes.") - - # Verify bytes sent from ReceiveBridge match expected_bytes - if sent_bytes != bytes: - raise ValueError(f"Received {sent_bytes} instead of {bytes}.") - - -@simulate(bridge_tx) -async def test_some_random_values(ctx): - for i in sample(range(0xFFFF), k=5000): - expected = f"D{i:04X}\r\n".encode("ascii") - await verify_encoding(ctx, i, expected)