diff --git a/README.md b/README.md index 7e16a5c..3a02d2b 100644 --- a/README.md +++ b/README.md @@ -1,10 +1,11 @@ -![](doc/assets/manta.png) +![](doc/assets/logo.png) ## Manta: An In-Situ Debugging Tool for Programmable Hardware ![functional_simulation](https://github.com/fischermoseley/manta/actions/workflows/functional_simulation.yml/badge.svg) ![formal_verification](https://github.com/fischermoseley/manta/actions/workflows/formal_verification.yml/badge.svg) ![build_examples](https://github.com/fischermoseley/manta/actions/workflows/build_examples.yml/badge.svg) ![build_docs](https://github.com/fischermoseley/manta/actions/workflows/build_docs.yml/badge.svg) + [![License: GPL v3](https://img.shields.io/badge/License-GPLv3-blue.svg)](https://www.gnu.org/licenses/gpl-3.0) [![Code style: black](https://img.shields.io/badge/code%20style-black-000000.svg)](https://github.com/psf/black) diff --git a/doc/assets/io_core_block_diagram.png b/doc/assets/io_core_architecture.png similarity index 100% rename from doc/assets/io_core_block_diagram.png rename to doc/assets/io_core_architecture.png diff --git a/doc/assets/manta_logic_analyzer_architecture.png b/doc/assets/logic_analyzer_architecture.png similarity index 100% rename from doc/assets/manta_logic_analyzer_architecture.png rename to doc/assets/logic_analyzer_architecture.png diff --git a/doc/assets/manta.png b/doc/assets/logo.png similarity index 100% rename from doc/assets/manta.png rename to doc/assets/logo.png diff --git a/doc/assets/manta_minimal_border.png b/doc/assets/logo_minimal_border.png similarity index 100% rename from doc/assets/manta_minimal_border.png rename to doc/assets/logo_minimal_border.png diff --git a/doc/assets/manta_ray.png b/doc/assets/logo_ray_only.png similarity index 100% rename from doc/assets/manta_ray.png rename to doc/assets/logo_ray_only.png diff --git a/doc/assets/manta_transparency.png b/doc/assets/logo_ray_only_transparent.png similarity index 100% rename from doc/assets/manta_transparency.png rename to doc/assets/logo_ray_only_transparent.png diff --git a/doc/assets/manta_with_shadow.png b/doc/assets/logo_ray_only_with_shadow.png similarity index 100% rename from doc/assets/manta_with_shadow.png rename to doc/assets/logo_ray_only_with_shadow.png diff --git a/doc/assets/ps2.jpeg b/doc/assets/ps2.jpeg deleted file mode 100644 index cda9a5c..0000000 Binary files a/doc/assets/ps2.jpeg and /dev/null differ diff --git a/doc/index.md b/doc/index.md index f35eb8b..b3c88f9 100644 --- a/doc/index.md +++ b/doc/index.md @@ -1,4 +1,4 @@ -![](assets/manta.png) +![](assets/logo.png) ## Manta: An In-Situ Debugging Tool for Programmable Hardware diff --git a/doc/io_core.md b/doc/io_core.md index 0bed863..991c162 100644 --- a/doc/io_core.md +++ b/doc/io_core.md @@ -97,7 +97,7 @@ While the IO core performs a very, very simple task, it carries a few caveats. This is done with the architecture shown below: -![](assets/io_core_block_diagram.png){:style="width:49%"} +![](assets/io_core_architecture.png){:style="width:49%"} Each of the probes is mapped to a register of Manta's internal memory. Since Manta's internal registers are 16 bits wide, probes less than 16 bits are mapped to a single register, but probes wider than 16 bits require multiple. diff --git a/doc/logic_analyzer_core.md b/doc/logic_analyzer_core.md index 0ad19ad..edd9d50 100644 --- a/doc/logic_analyzer_core.md +++ b/doc/logic_analyzer_core.md @@ -139,7 +139,7 @@ At present, this class contains methods used really only for capturing data, and ## How It Works The Logic Analyzer Core's implementation on the FPGA consists of three primary components: -![](assets/manta_logic_analyzer_architecture.png){style="width:85%"} +![](assets/logic_analyzer_architecture.png){style="width:85%"} - The _Finite State Machine (FSM)_, which controls the operation of the core. The FSM's operation is driven by its associated registers, which are placed in a separate module. This permits simple CDC between the bus and user clock domains. - The _Trigger Block_, which generates the core's trigger condition. The trigger block contains a trigger for each input probe, and the registers necessary to configure them. It also contains the $N$-logic gate (either AND or OR) that generates the core's trigger from the individual probe triggers. CDC is performed in exactly the same manner as the FSM. If an external trigger is specified, the trigger block is omitted from the Logic Analyzer Core, and the external trigger is routed to the FSM's `trig` input. diff --git a/mkdocs.yml b/mkdocs.yml index b43cd2a..0da55bc 100644 --- a/mkdocs.yml +++ b/mkdocs.yml @@ -8,8 +8,8 @@ docs_dir: 'doc' theme: name: material - logo: assets/manta_minimal_border.png - favicon: assets/manta_with_shadow.png + logo: assets/logo_minimal_border.png + favicon: assets/logo_ray_only_with_shadow.png features: - content.code.copy - content.code.annotate