From 3d722d1e60e86e3f356b1362868f36c029ce39dd Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 27 Aug 2023 12:12:25 -0700 Subject: [PATCH] fix nasty addressing bug in block_memory --- src/manta/block_mem_core/block_memory.v | 8 ++++---- src/manta/la_core/__init__.py | 2 +- src/manta/la_core/logic_analyzer_controller.v | 5 ++++- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/src/manta/block_mem_core/block_memory.v b/src/manta/block_mem_core/block_memory.v index 006df1e..ae00f17 100644 --- a/src/manta/block_mem_core/block_memory.v +++ b/src/manta/block_mem_core/block_memory.v @@ -75,14 +75,14 @@ module block_memory ( // throw BRAM operations into the front of the pipeline wea <= 0; if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= MAX_ADDR)) begin - wea[addr_i % N_BRAMS] <= rw_i; - addra[addr_i % N_BRAMS] <= (addr_i - BASE_ADDR) / N_BRAMS; - dina[addr_i % N_BRAMS] <= data_i; + wea[(addr_i - BASE_ADDR) % N_BRAMS] <= rw_i; + addra[(addr_i - BASE_ADDR) % N_BRAMS] <= (addr_i - BASE_ADDR) / N_BRAMS; + dina[(addr_i - BASE_ADDR) % N_BRAMS] <= data_i; end // pull BRAM reads from the back of the pipeline if( (valid_pipe[2]) && (addr_pipe[2] >= BASE_ADDR) && (addr_pipe[2] <= MAX_ADDR)) begin - data_o <= douta[addr_pipe[2] % N_BRAMS]; + data_o <= douta[(addr_pipe[2] - BASE_ADDR) % N_BRAMS]; end end diff --git a/src/manta/la_core/__init__.py b/src/manta/la_core/__init__.py index e8963b9..0e78ebf 100644 --- a/src/manta/la_core/__init__.py +++ b/src/manta/la_core/__init__.py @@ -75,7 +75,7 @@ class LogicAnalyzerCore: # compute base addresses self.fsm_base_addr = self.base_addr - self.trigger_block_base_addr = self.fsm_base_addr + 6 + self.trigger_block_base_addr = self.fsm_base_addr + 7 self.total_probe_width = sum(self.probes.values()) n_brams = math.ceil(self.total_probe_width / 16) diff --git a/src/manta/la_core/logic_analyzer_controller.v b/src/manta/la_core/logic_analyzer_controller.v index 8b2224e..50c90bf 100644 --- a/src/manta/la_core/logic_analyzer_controller.v +++ b/src/manta/la_core/logic_analyzer_controller.v @@ -63,7 +63,10 @@ module logic_analyzer_controller ( write_pointer <= write_pointer + 1; bram_we <= 1; - if(write_pointer == trigger_loc) state <= IN_POSITION; + if(write_pointer == trigger_loc) begin + if(trig) state <= CAPTURING; + else state <= IN_POSITION; + end end else if(state == IN_POSITION) begin