diff --git a/environment.sh b/.env similarity index 100% rename from environment.sh rename to .env diff --git a/.github/workflows/run_tests.yml b/.github/workflows/run_tests.yml index 6f07cb5..0f76ba3 100644 --- a/.github/workflows/run_tests.yml +++ b/.github/workflows/run_tests.yml @@ -19,7 +19,7 @@ jobs: - name: Run tests run: | - source ./environment.sh + source .env uv run make test - name: Upload coverage reports diff --git a/.gitignore b/.gitignore index 77156ab..29854a6 100644 --- a/.gitignore +++ b/.gitignore @@ -11,25 +11,11 @@ __pycache__/ build/ dist/ +# Autogenerated Manta source +manta.v + # Miscellaneous file types -*.v -*.sv *.vcd -*.out *.csv *.xml .coverage* - -# Vivado files -*.log -*.jou -*.rpt -*.bin -*.bit -*.out -.Xil/ - -# Yosys/IceStorm files -*.asc -*.bin -*.json diff --git a/examples/common/.gitignore b/examples/common/.gitignore deleted file mode 100644 index 8365015..0000000 --- a/examples/common/.gitignore +++ /dev/null @@ -1 +0,0 @@ -!divider.sv diff --git a/examples/common/build.tcl b/examples/common/build.tcl new file mode 100644 index 0000000..1d7ae16 --- /dev/null +++ b/examples/common/build.tcl @@ -0,0 +1,35 @@ +#!/usr/bin/tclsh + +set partNum xc7a100tcsg324-1 + +read_verilog -sv [ glob ../*.{sv,v,svh,vh} ] +read_xdc ../top_level.xdc + +set_part $partNum + +# synth +synth_design -top top_level -part $partNum -verbose +report_utilization -file post_synth_util.rpt +report_timing_summary -file post_synth_timing_summary.rpt +report_timing -file post_synth_timing.rpt + +# place +opt_design +place_design +phys_opt_design +report_utilization -file post_place_util.rpt + +report_clock_utilization -file clock_util.rpt +report_timing_summary -file post_place_timing_summary.rpt +report_timing -file post_place_timing.rpt + +# route design and generate bitstream +route_design -directive Explore +write_bitstream -force out.bit + +report_route_status -file post_route_status.rpt +report_timing_summary -file post_route_timing_summary.rpt +report_timing -file post_route_timing.rpt +report_power -file post_route_power.rpt +report_drc -file post_imp_drc.rpt +write_verilog -force cpu_impl_netlist.v -mode timesim -sdf_anno true diff --git a/examples/common/build_ice40.sh b/examples/common/build_ice40.sh new file mode 100755 index 0000000..115ac0d --- /dev/null +++ b/examples/common/build_ice40.sh @@ -0,0 +1,21 @@ +#!/usr/bin/env bash +set -euo pipefail + +# shellcheck source=examples/common/find_tool.sh +source "$(dirname "$(readlink -f "$0")")/find_tool.sh" + +# Make sure tools are accessible +YOSYS_CMD=$(find_tool yosys) +NEXTPNR_ICE40_CMD=$(find_tool nextpnr-ice40) +ICEPACK_CMD=$(find_tool icepack) + +# Generate Verilog source for Manta +python3 -m manta gen manta.yaml manta.v + +# Clean build/ directory, and run tools from within it +rm -rf build/ +mkdir -p build/ +cd build +$YOSYS_CMD -p 'synth_ice40 -top top_level -json top_level.json' ../top_level.sv +$NEXTPNR_ICE40_CMD --hx1k --json top_level.json --pcf ../top_level.pcf --asc top_level.asc +$ICEPACK_CMD top_level.asc top_level.bin diff --git a/examples/common/build_vivado.sh b/examples/common/build_vivado.sh new file mode 100755 index 0000000..d170577 --- /dev/null +++ b/examples/common/build_vivado.sh @@ -0,0 +1,17 @@ +#!/usr/bin/env bash +set -euo pipefail + +# shellcheck source=examples/common/find_tool.sh +source "$(dirname "$(readlink -f "$0")")/find_tool.sh" + +# Make sure Vivado is accessible +VIVADO_CMD=$(find_tool vivado) + +# Generate Verilog source for Manta +python3 -m manta gen manta.yaml manta.v + +# Clean build/ directory, and run Vivado from within it +rm -rf build/ +mkdir -p build/ +cd build +$VIVADO_CMD -mode batch -source ../../../../common/build.tcl diff --git a/examples/common/find_tool.sh b/examples/common/find_tool.sh new file mode 100644 index 0000000..0588790 --- /dev/null +++ b/examples/common/find_tool.sh @@ -0,0 +1,35 @@ +#!/usr/bin/env bash + +# Find a tool binary from either the $PATH environment variable, or another +# environment variable named after the tool (ie, $VIVADO or $YOSYS). +# Usage: find_tool +# The environment variable is the uppercased tool name, with any hyphens converted to underscores. +# Prints the command to use, or exits with an error. +find_tool() { + local tool="$1" + local env_var + env_var=$(echo "$tool" | tr '[:lower:]' '[:upper:]') + env_var="${env_var//-/_}" + local on_path=false + local env_set=false + + if command -v "$tool" &> /dev/null; then + on_path=true + fi + + if [[ -n "${!env_var+x}" ]]; then + env_set=true + fi + + if $on_path && $env_set; then + echo "Error: Both \$$env_var is set and '$tool' is on PATH. Please use only one." >&2 + exit 1 + elif $on_path; then + echo "$tool" + elif $env_set; then + echo "${!env_var}" + else + echo "Error: $tool not found. Either set \$$env_var environment variable or add '$tool' to PATH." >&2 + exit 1 + fi +} diff --git a/examples/verilog/icestick/uart_io_core/.gitignore b/examples/verilog/icestick/uart_io_core/.gitignore deleted file mode 100644 index 1e11c14..0000000 --- a/examples/verilog/icestick/uart_io_core/.gitignore +++ /dev/null @@ -1 +0,0 @@ -!top_level.sv diff --git a/examples/verilog/icestick/uart_io_core/build.sh b/examples/verilog/icestick/uart_io_core/build.sh deleted file mode 100755 index 78b10b9..0000000 --- a/examples/verilog/icestick/uart_io_core/build.sh +++ /dev/null @@ -1,7 +0,0 @@ -#!/usr/bin/env bash -set -e - -python3 -m manta gen manta.yaml manta.v -$YOSYS -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv -$NEXTPNR_ICE40 --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc -$ICEPACK top_level.asc top_level.bin diff --git a/examples/verilog/icestick/uart_io_core/build.sh b/examples/verilog/icestick/uart_io_core/build.sh new file mode 120000 index 0000000..8860b0d --- /dev/null +++ b/examples/verilog/icestick/uart_io_core/build.sh @@ -0,0 +1 @@ +../../../common/build_ice40.sh \ No newline at end of file diff --git a/examples/verilog/icestick/uart_logic_analyzer/.gitignore b/examples/verilog/icestick/uart_logic_analyzer/.gitignore deleted file mode 100644 index 1e11c14..0000000 --- a/examples/verilog/icestick/uart_logic_analyzer/.gitignore +++ /dev/null @@ -1 +0,0 @@ -!top_level.sv diff --git a/examples/verilog/icestick/uart_logic_analyzer/build.sh b/examples/verilog/icestick/uart_logic_analyzer/build.sh deleted file mode 100755 index 78b10b9..0000000 --- a/examples/verilog/icestick/uart_logic_analyzer/build.sh +++ /dev/null @@ -1,7 +0,0 @@ -#!/usr/bin/env bash -set -e - -python3 -m manta gen manta.yaml manta.v -$YOSYS -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv -$NEXTPNR_ICE40 --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc -$ICEPACK top_level.asc top_level.bin diff --git a/examples/verilog/icestick/uart_logic_analyzer/build.sh b/examples/verilog/icestick/uart_logic_analyzer/build.sh new file mode 120000 index 0000000..8860b0d --- /dev/null +++ b/examples/verilog/icestick/uart_logic_analyzer/build.sh @@ -0,0 +1 @@ +../../../common/build_ice40.sh \ No newline at end of file diff --git a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/.gitignore b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/.gitignore deleted file mode 100644 index 0245c4b..0000000 --- a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -!top_level.sv -!divider.sv diff --git a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh deleted file mode 100755 index 591adda..0000000 --- a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh +++ /dev/null @@ -1,6 +0,0 @@ -#!/usr/bin/env bash -set -e - -python3 -m manta gen manta.yaml manta.v -mkdir -p build/ -$VIVADO -mode batch -source build.tcl diff --git a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh new file mode 120000 index 0000000..fdafb65 --- /dev/null +++ b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh @@ -0,0 +1 @@ +../../../common/build_vivado.sh \ No newline at end of file diff --git a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.tcl b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.tcl deleted file mode 100644 index 0e7570e..0000000 --- a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.tcl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/tclsh - -set partNum xc7a100tcsg324-1 -set outputDir build - -read_verilog -sv [ glob *.{sv,v,svh,vh} ] -read_xdc top_level.xdc - -set_part $partNum - -# synth -synth_design -top top_level -part $partNum -verbose -report_utilization -file $outputDir/post_synth_util.rpt -report_timing_summary -file $outputDir/post_synth_timing_summary.rpt -report_timing -file $outputDir/post_synth_timing.rpt - -# place -opt_design -place_design -phys_opt_design -report_utilization -file $outputDir/post_place_util.rpt - -report_clock_utilization -file $outputDir/clock_util.rpt -report_timing_summary -file $outputDir/post_place_timing_summary.rpt -report_timing -file $outputDir/post_place_timing.rpt - -# route design and generate bitstream -route_design -directive Explore -write_bitstream -force $outputDir/out.bit - -report_route_status -file $outputDir/post_route_status.rpt -report_timing_summary -file $outputDir/post_route_timing_summary.rpt -report_timing -file $outputDir/post_route_timing.rpt -report_power -file $outputDir/post_route_power.rpt -report_drc -file $outputDir/post_imp_drc.rpt -write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true diff --git a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/.gitignore b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/.gitignore deleted file mode 100644 index 1e11c14..0000000 --- a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/.gitignore +++ /dev/null @@ -1 +0,0 @@ -!top_level.sv diff --git a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh deleted file mode 100755 index 591adda..0000000 --- a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh +++ /dev/null @@ -1,6 +0,0 @@ -#!/usr/bin/env bash -set -e - -python3 -m manta gen manta.yaml manta.v -mkdir -p build/ -$VIVADO -mode batch -source build.tcl diff --git a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh new file mode 120000 index 0000000..fdafb65 --- /dev/null +++ b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh @@ -0,0 +1 @@ +../../../common/build_vivado.sh \ No newline at end of file diff --git a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.tcl b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.tcl deleted file mode 100644 index 0e7570e..0000000 --- a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.tcl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/tclsh - -set partNum xc7a100tcsg324-1 -set outputDir build - -read_verilog -sv [ glob *.{sv,v,svh,vh} ] -read_xdc top_level.xdc - -set_part $partNum - -# synth -synth_design -top top_level -part $partNum -verbose -report_utilization -file $outputDir/post_synth_util.rpt -report_timing_summary -file $outputDir/post_synth_timing_summary.rpt -report_timing -file $outputDir/post_synth_timing.rpt - -# place -opt_design -place_design -phys_opt_design -report_utilization -file $outputDir/post_place_util.rpt - -report_clock_utilization -file $outputDir/clock_util.rpt -report_timing_summary -file $outputDir/post_place_timing_summary.rpt -report_timing -file $outputDir/post_place_timing.rpt - -# route design and generate bitstream -route_design -directive Explore -write_bitstream -force $outputDir/out.bit - -report_route_status -file $outputDir/post_route_status.rpt -report_timing_summary -file $outputDir/post_route_timing_summary.rpt -report_timing -file $outputDir/post_route_timing.rpt -report_power -file $outputDir/post_route_power.rpt -report_drc -file $outputDir/post_imp_drc.rpt -write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true diff --git a/examples/verilog/nexys4_ddr/uart_io_core/.gitignore b/examples/verilog/nexys4_ddr/uart_io_core/.gitignore deleted file mode 100644 index 1e11c14..0000000 --- a/examples/verilog/nexys4_ddr/uart_io_core/.gitignore +++ /dev/null @@ -1 +0,0 @@ -!top_level.sv diff --git a/examples/verilog/nexys4_ddr/uart_io_core/build.sh b/examples/verilog/nexys4_ddr/uart_io_core/build.sh deleted file mode 100755 index 591adda..0000000 --- a/examples/verilog/nexys4_ddr/uart_io_core/build.sh +++ /dev/null @@ -1,6 +0,0 @@ -#!/usr/bin/env bash -set -e - -python3 -m manta gen manta.yaml manta.v -mkdir -p build/ -$VIVADO -mode batch -source build.tcl diff --git a/examples/verilog/nexys4_ddr/uart_io_core/build.sh b/examples/verilog/nexys4_ddr/uart_io_core/build.sh new file mode 120000 index 0000000..fdafb65 --- /dev/null +++ b/examples/verilog/nexys4_ddr/uart_io_core/build.sh @@ -0,0 +1 @@ +../../../common/build_vivado.sh \ No newline at end of file diff --git a/examples/verilog/nexys4_ddr/uart_io_core/build.tcl b/examples/verilog/nexys4_ddr/uart_io_core/build.tcl deleted file mode 100644 index 0e7570e..0000000 --- a/examples/verilog/nexys4_ddr/uart_io_core/build.tcl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/tclsh - -set partNum xc7a100tcsg324-1 -set outputDir build - -read_verilog -sv [ glob *.{sv,v,svh,vh} ] -read_xdc top_level.xdc - -set_part $partNum - -# synth -synth_design -top top_level -part $partNum -verbose -report_utilization -file $outputDir/post_synth_util.rpt -report_timing_summary -file $outputDir/post_synth_timing_summary.rpt -report_timing -file $outputDir/post_synth_timing.rpt - -# place -opt_design -place_design -phys_opt_design -report_utilization -file $outputDir/post_place_util.rpt - -report_clock_utilization -file $outputDir/clock_util.rpt -report_timing_summary -file $outputDir/post_place_timing_summary.rpt -report_timing -file $outputDir/post_place_timing.rpt - -# route design and generate bitstream -route_design -directive Explore -write_bitstream -force $outputDir/out.bit - -report_route_status -file $outputDir/post_route_status.rpt -report_timing_summary -file $outputDir/post_route_timing_summary.rpt -report_timing -file $outputDir/post_route_timing.rpt -report_power -file $outputDir/post_route_power.rpt -report_drc -file $outputDir/post_imp_drc.rpt -write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true diff --git a/examples/verilog/nexys4_ddr/uart_logic_analyzer/.gitignore b/examples/verilog/nexys4_ddr/uart_logic_analyzer/.gitignore deleted file mode 100644 index 1e11c14..0000000 --- a/examples/verilog/nexys4_ddr/uart_logic_analyzer/.gitignore +++ /dev/null @@ -1 +0,0 @@ -!top_level.sv diff --git a/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh b/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh deleted file mode 100755 index 591adda..0000000 --- a/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh +++ /dev/null @@ -1,6 +0,0 @@ -#!/usr/bin/env bash -set -e - -python3 -m manta gen manta.yaml manta.v -mkdir -p build/ -$VIVADO -mode batch -source build.tcl diff --git a/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh b/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh new file mode 120000 index 0000000..fdafb65 --- /dev/null +++ b/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh @@ -0,0 +1 @@ +../../../common/build_vivado.sh \ No newline at end of file diff --git a/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.tcl b/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.tcl deleted file mode 100644 index 0e7570e..0000000 --- a/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.tcl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/tclsh - -set partNum xc7a100tcsg324-1 -set outputDir build - -read_verilog -sv [ glob *.{sv,v,svh,vh} ] -read_xdc top_level.xdc - -set_part $partNum - -# synth -synth_design -top top_level -part $partNum -verbose -report_utilization -file $outputDir/post_synth_util.rpt -report_timing_summary -file $outputDir/post_synth_timing_summary.rpt -report_timing -file $outputDir/post_synth_timing.rpt - -# place -opt_design -place_design -phys_opt_design -report_utilization -file $outputDir/post_place_util.rpt - -report_clock_utilization -file $outputDir/clock_util.rpt -report_timing_summary -file $outputDir/post_place_timing_summary.rpt -report_timing -file $outputDir/post_place_timing.rpt - -# route design and generate bitstream -route_design -directive Explore -write_bitstream -force $outputDir/out.bit - -report_route_status -file $outputDir/post_route_status.rpt -report_timing_summary -file $outputDir/post_route_timing_summary.rpt -report_timing -file $outputDir/post_route_timing.rpt -report_power -file $outputDir/post_route_power.rpt -report_drc -file $outputDir/post_imp_drc.rpt -write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true