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manta
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squash data duplication bug

This commit is contained in:
Fischer Moseley 2023-04-16 17:55:13 -04:00
parent 320638508d
commit 3400ea63c8
1 changed files with 4 additions and 2 deletions
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6
src/manta/__init__.py
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@ -249,8 +249,10 @@ class UARTInterface:
for i in range(0, len(addrs), self.chunk_size): for i in range(0, len(addrs), self.chunk_size):
addr_chunk = addrs[i:i+self.chunk_size] addr_chunk = addrs[i:i+self.chunk_size]
data_chunk = datas[i:i+self.chunk_size]
outbound_bytes = [f"M{addrs[i]:04X}{datas[i]:04X}\r\n" for i in range(len(addr_chunk))]
outbound_bytes = [f"M{a:04X}{d:04X}\r\n" for a, d in zip(addr_chunk, data_chunk)]
outbound_bytes = [ob.encode('ascii') for ob in outbound_bytes] outbound_bytes = [ob.encode('ascii') for ob in outbound_bytes]
outbound_bytes = b"".join(outbound_bytes) outbound_bytes = b"".join(outbound_bytes)
@ -1152,7 +1154,7 @@ def main():
Supported commands: Supported commands:
gen [config file] [path] generate a verilog module with the given configuration, and save to the provided path gen [config file] [path] generate a verilog module with the given configuration, and save to the provided path
capture [config file] [LA core] [path] [path] start a capture on the specified core, and save the results to a .mem or .vcd file at the provided path capture [config file] [LA core] [path] [path] start a capture on the specified core, and save the results to a .mem or .vcd file at the provided path(s)
playback [config file] [LA core] [path] generate a verilog module that plays back a capture from a given logic analyzer core, and save to the provided path playback [config file] [LA core] [path] generate a verilog module that plays back a capture from a given logic analyzer core, and save to the provided path
ports list all available serial ports ports list all available serial ports
help, ray display this splash screen (hehe...splash screen) help, ray display this splash screen (hehe...splash screen)