From 3400ea63c81ab017eb90a4e005bacbdeff849b74 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 16 Apr 2023 17:55:13 -0400 Subject: [PATCH] squash data duplication bug --- src/manta/__init__.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/manta/__init__.py b/src/manta/__init__.py index b98ef6d..8e9dc3f 100644 --- a/src/manta/__init__.py +++ b/src/manta/__init__.py @@ -249,8 +249,10 @@ class UARTInterface: for i in range(0, len(addrs), self.chunk_size): addr_chunk = addrs[i:i+self.chunk_size] + data_chunk = datas[i:i+self.chunk_size] - outbound_bytes = [f"M{addrs[i]:04X}{datas[i]:04X}\r\n" for i in range(len(addr_chunk))] + + outbound_bytes = [f"M{a:04X}{d:04X}\r\n" for a, d in zip(addr_chunk, data_chunk)] outbound_bytes = [ob.encode('ascii') for ob in outbound_bytes] outbound_bytes = b"".join(outbound_bytes) @@ -1152,7 +1154,7 @@ def main(): Supported commands: gen [config file] [path] generate a verilog module with the given configuration, and save to the provided path - capture [config file] [LA core] [path] [path] start a capture on the specified core, and save the results to a .mem or .vcd file at the provided path + capture [config file] [LA core] [path] [path] start a capture on the specified core, and save the results to a .mem or .vcd file at the provided path(s) playback [config file] [LA core] [path] generate a verilog module that plays back a capture from a given logic analyzer core, and save to the provided path ports list all available serial ports help, ray display this splash screen (hehe...splash screen)