tests: run in parallel with pytest-xdist

Makefile

@@ -1,6 +1,6 @@
 .PHONY: test format clean serve_docs
 test:
-	python3 -m pytest --cov-report xml --cov=src/manta
+	python3 -m pytest -n auto --dist loadgroup --cov-report xml --cov=src/manta
 
 format:
 	python3 -m ruff check --select I --fix

test/test_ethernet_interface.py

@@ -104,6 +104,7 @@ class EthernetMemoryCoreTest(Elaboratable):
                 )
 
 
+@pytest.mark.xdist_group(name="nexys4ddr")
 @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
 def test_mem_core_xilinx():
     EthernetMemoryCoreTest(Nexys4DDRPlatform()).verify()

test/test_io_core_hw.py

@@ -108,12 +108,14 @@ class IOCoreLoopbackTest(Elaboratable):
         self.verify_probes_update()
 
 
+@pytest.mark.xdist_group(name="nexys4ddr")
 @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
 def test_output_probe_initial_values_xilinx():
     port = os.environ["NEXYS4DDR_PORT"]
     IOCoreLoopbackTest(Nexys4DDRPlatform(), port).verify()
 
 
+@pytest.mark.xdist_group(name="icestick")
 @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed")
 def test_output_probe_initial_values_ice40():
     port = os.environ["ICESTICK_PORT"]

test/test_logic_analyzer_hw.py

@@ -79,12 +79,14 @@ class LogicAnalyzerCounterTest(Elaboratable):
                     raise ValueError("Bad counter!")
 
 
+@pytest.mark.xdist_group(name="nexys4ddr")
 @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
 def test_logic_analyzer_core_xilinx():
     port = os.environ["NEXYS4DDR_PORT"]
     LogicAnalyzerCounterTest(Nexys4DDRPlatform(), port).verify()
 
 
+@pytest.mark.xdist_group(name="icestick")
 @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed")
 def test_logic_analyzer_core_ice40():
     port = os.environ["ICESTICK_PORT"]

test/test_mem_core_hw.py

@@ -111,6 +111,7 @@ depths = [2, 512, 1024]
 nexys4ddr_cases = [(m, w, d) for m in modes for w in widths for d in depths]
 
 
+@pytest.mark.xdist_group(name="nexys4ddr")
 @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
 @pytest.mark.parametrize("mode, width, depth", nexys4ddr_cases)
 def test_mem_core_xilinx(mode, width, depth):
@@ -125,6 +126,7 @@ depths = [2, 512, 1024]
 ice40_cases = [(m, w, d) for m in modes for w in widths for d in depths]
 
 
+@pytest.mark.xdist_group(name="icestick")
 @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed")
 @pytest.mark.parametrize("mode, width, depth", ice40_cases)
 def test_mem_core_ice40(mode, width, depth):

test/test_mem_core_sim.py

@@ -259,9 +259,9 @@ class MemoryCoreTests:
 
 
 modes = ["bidirectional", "fpga_to_host", "host_to_fpga"]
-widths = [23, randint(0, 128)]
-depths = [512, randint(0, 1024)]
-base_addrs = [0, randint(0, 32678)]
+widths = [23, 121]
+depths = [512, 968]
+base_addrs = [0, 32313]
 
 cases = [
     (m, w, d, ba) for m in modes for w in widths for d in depths for ba in base_addrs

test/test_uart_baud_mismatch.py

@@ -88,6 +88,7 @@ nexys4ddr_pass_cases = [
 ]
 
 
+@pytest.mark.xdist_group(name="nexys4ddr")
 @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
 @pytest.mark.parametrize(
     "baudrate, percent_slowdown, stall_interval", nexys4ddr_pass_cases
@@ -108,6 +109,7 @@ nexys4ddr_fail_cases = [
 ]
 
 
+@pytest.mark.xdist_group(name="icestick")
 @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
 @pytest.mark.parametrize(
     "baudrate, percent_slowdown, stall_interval", nexys4ddr_fail_cases