From 255c4522069a0234dc250d520eabecacdc93707d Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Sun, 6 Apr 2025 21:52:43 -0700
Subject: [PATCH] tests: run in parallel with pytest-xdist

---
 Makefile                        | 2 +-
 test/test_ethernet_interface.py | 1 +
 test/test_io_core_hw.py         | 2 ++
 test/test_logic_analyzer_hw.py  | 2 ++
 test/test_mem_core_hw.py        | 2 ++
 test/test_mem_core_sim.py       | 6 +++---
 test/test_uart_baud_mismatch.py | 2 ++
 7 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/Makefile b/Makefile
index 3d52e68..6e1e6ef 100644
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,6 @@
 .PHONY: test format clean serve_docs
 test:
-	python3 -m pytest --cov-report xml --cov=src/manta
+	python3 -m pytest -n auto --dist loadgroup --cov-report xml --cov=src/manta
 
 format:
 	python3 -m ruff check --select I --fix
diff --git a/test/test_ethernet_interface.py b/test/test_ethernet_interface.py
index c71bd1c..4bd3514 100644
--- a/test/test_ethernet_interface.py
+++ b/test/test_ethernet_interface.py
@@ -104,6 +104,7 @@ class EthernetMemoryCoreTest(Elaboratable):
                 )
 
 
+@pytest.mark.xdist_group(name="nexys4ddr")
 @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
 def test_mem_core_xilinx():
     EthernetMemoryCoreTest(Nexys4DDRPlatform()).verify()
diff --git a/test/test_io_core_hw.py b/test/test_io_core_hw.py
index ea5645b..ebccc5e 100644
--- a/test/test_io_core_hw.py
+++ b/test/test_io_core_hw.py
@@ -108,12 +108,14 @@ class IOCoreLoopbackTest(Elaboratable):
         self.verify_probes_update()
 
 
+@pytest.mark.xdist_group(name="nexys4ddr")
 @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
 def test_output_probe_initial_values_xilinx():
     port = os.environ["NEXYS4DDR_PORT"]
     IOCoreLoopbackTest(Nexys4DDRPlatform(), port).verify()
 
 
+@pytest.mark.xdist_group(name="icestick")
 @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed")
 def test_output_probe_initial_values_ice40():
     port = os.environ["ICESTICK_PORT"]
diff --git a/test/test_logic_analyzer_hw.py b/test/test_logic_analyzer_hw.py
index 16678d8..fc338c7 100644
--- a/test/test_logic_analyzer_hw.py
+++ b/test/test_logic_analyzer_hw.py
@@ -79,12 +79,14 @@ class LogicAnalyzerCounterTest(Elaboratable):
                     raise ValueError("Bad counter!")
 
 
+@pytest.mark.xdist_group(name="nexys4ddr")
 @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
 def test_logic_analyzer_core_xilinx():
     port = os.environ["NEXYS4DDR_PORT"]
     LogicAnalyzerCounterTest(Nexys4DDRPlatform(), port).verify()
 
 
+@pytest.mark.xdist_group(name="icestick")
 @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed")
 def test_logic_analyzer_core_ice40():
     port = os.environ["ICESTICK_PORT"]
diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py
index a8e2c28..1d5d15a 100644
--- a/test/test_mem_core_hw.py
+++ b/test/test_mem_core_hw.py
@@ -111,6 +111,7 @@ depths = [2, 512, 1024]
 nexys4ddr_cases = [(m, w, d) for m in modes for w in widths for d in depths]
 
 
+@pytest.mark.xdist_group(name="nexys4ddr")
 @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
 @pytest.mark.parametrize("mode, width, depth", nexys4ddr_cases)
 def test_mem_core_xilinx(mode, width, depth):
@@ -125,6 +126,7 @@ depths = [2, 512, 1024]
 ice40_cases = [(m, w, d) for m in modes for w in widths for d in depths]
 
 
+@pytest.mark.xdist_group(name="icestick")
 @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed")
 @pytest.mark.parametrize("mode, width, depth", ice40_cases)
 def test_mem_core_ice40(mode, width, depth):
diff --git a/test/test_mem_core_sim.py b/test/test_mem_core_sim.py
index 05b36bd..90aef83 100644
--- a/test/test_mem_core_sim.py
+++ b/test/test_mem_core_sim.py
@@ -259,9 +259,9 @@ class MemoryCoreTests:
 
 
 modes = ["bidirectional", "fpga_to_host", "host_to_fpga"]
-widths = [23, randint(0, 128)]
-depths = [512, randint(0, 1024)]
-base_addrs = [0, randint(0, 32678)]
+widths = [23, 121]
+depths = [512, 968]
+base_addrs = [0, 32313]
 
 cases = [
     (m, w, d, ba) for m in modes for w in widths for d in depths for ba in base_addrs
diff --git a/test/test_uart_baud_mismatch.py b/test/test_uart_baud_mismatch.py
index 40a6ec3..0fb9629 100644
--- a/test/test_uart_baud_mismatch.py
+++ b/test/test_uart_baud_mismatch.py
@@ -88,6 +88,7 @@ nexys4ddr_pass_cases = [
 ]
 
 
+@pytest.mark.xdist_group(name="nexys4ddr")
 @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
 @pytest.mark.parametrize(
     "baudrate, percent_slowdown, stall_interval", nexys4ddr_pass_cases
@@ -108,6 +109,7 @@ nexys4ddr_fail_cases = [
 ]
 
 
+@pytest.mark.xdist_group(name="icestick")
 @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
 @pytest.mark.parametrize(
     "baudrate, percent_slowdown, stall_interval", nexys4ddr_fail_cases