uart: use new datapath, reimplement read/write methods, revert to old connectivity approach
This commit is contained in:
Fischer Moseley
parent
6888b4ded5
commit
1805efa85d
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@ -13,9 +13,6 @@ class MemoryCore(MantaCore):
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and the other provided to user logic.
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"""
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bus_source: Out(InternalBusSignature)
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bus_sink: In(InternalBusSignature)
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def __init__(self, mode, width, depth):
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"""
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Create a Memory Core with the given width and depth.
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@ -36,28 +33,46 @@ class MemoryCore(MantaCore):
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depth (int): The depth of the memory, in entries.
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"""
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super().__init__()
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self._mode = mode
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self._width = width
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self._depth = depth
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self._n_mems = ceil(self._width / 32)
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# Bus Connections
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self.bus_i = Signal(InternalBusLayout)
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self.bus_o = Signal(InternalBusLayout)
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# User Ports
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if self._mode == "fpga_to_host":
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self.user_addr = Signal(range(self._depth))
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self.user_data_in = Signal(self._width)
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self.user_write_enable = Signal()
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self._top_level_ports = [
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self.user_addr,
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self.user_data_in,
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self.user_write_enable,
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]
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elif self._mode == "host_to_fpga":
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self.user_addr = Signal(range(self._depth))
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self.user_data_out = Signal(self._width)
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self._top_level_ports = [
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self.user_addr,
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self.user_data_out,
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]
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elif self._mode == "bidirectional":
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self.user_addr = Signal(range(self._depth))
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self.user_data_in = Signal(self._width)
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self.user_data_out = Signal(self._width)
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self.user_write_enable = Signal()
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self._top_level_ports = [
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self.user_addr,
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self.user_data_in,
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self.user_data_out,
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self.user_write_enable,
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]
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# Define memories
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n_full = self._width // 32
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@ -69,6 +84,10 @@ class MemoryCore(MantaCore):
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if n_partial > 0:
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self._mems += [Memory(shape=n_partial, depth=self._depth, init=[0] * self._depth)]
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@property
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def top_level_ports(self):
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return self._top_level_ports
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@property
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def max_addr(self):
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return self.base_addr + (self._depth * self._n_mems)
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@ -133,11 +152,11 @@ class MemoryCore(MantaCore):
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# Throw BRAM operations into the front of the pipeline
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with m.If(
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(self.bus_sink.p.valid)
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& (self.bus_sink.p.addr >= start_addr)
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& (self.bus_sink.p.addr <= stop_addr)
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(self.bus_i.valid)
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& (self.bus_i.addr >= start_addr)
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& (self.bus_i.addr <= stop_addr)
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):
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m.d.sync += read_port.addr.eq(self.bus_sink.p.addr - start_addr)
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m.d.sync += read_port.addr.eq(self.bus_i.addr - start_addr)
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# Pull BRAM reads from the back of the pipeline
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with m.If(
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@ -146,7 +165,7 @@ class MemoryCore(MantaCore):
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& (self._bus_pipe[2].addr >= start_addr)
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& (self._bus_pipe[2].addr <= stop_addr)
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):
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m.d.sync += self.bus_source.p.data.eq(read_port.data)
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m.d.sync += self.bus_o.data.eq(read_port.data)
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elif self._mode == "host_to_fpga":
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write_port = mem.write_port()
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@ -154,13 +173,13 @@ class MemoryCore(MantaCore):
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# Throw BRAM operations into the front of the pipeline
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with m.If(
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(self.bus_sink.p.valid)
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& (self.bus_sink.p.addr >= start_addr)
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& (self.bus_sink.p.addr <= stop_addr)
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(self.bus_i.valid)
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& (self.bus_i.addr >= start_addr)
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& (self.bus_i.addr <= stop_addr)
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):
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m.d.sync += write_port.addr.eq(self.bus_sink.p.addr - start_addr)
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m.d.sync += write_port.data.eq(self.bus_sink.p.data)
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m.d.sync += write_port.en.eq(self.bus_sink.p.rw)
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m.d.sync += write_port.addr.eq(self.bus_i.addr - start_addr)
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m.d.sync += write_port.data.eq(self.bus_i.data)
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m.d.sync += write_port.en.eq(self.bus_i.rw)
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elif self._mode == "bidirectional":
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read_port = mem.read_port()
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@ -171,14 +190,14 @@ class MemoryCore(MantaCore):
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# Throw BRAM operations into the front of the pipeline
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with m.If(
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(self.bus_sink.p.valid)
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& (self.bus_sink.p.addr >= start_addr)
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& (self.bus_sink.p.addr <= stop_addr)
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(self.bus_i.valid)
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& (self.bus_i.addr >= start_addr)
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& (self.bus_i.addr <= stop_addr)
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):
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m.d.sync += read_port.addr.eq(self.bus_sink.p.addr - start_addr)
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m.d.sync += write_port.addr.eq(self.bus_sink.p.addr - start_addr)
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m.d.sync += write_port.data.eq(self.bus_sink.p.data)
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m.d.sync += write_port.en.eq(self.bus_sink.p.rw)
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m.d.sync += read_port.addr.eq(self.bus_i.addr - start_addr)
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m.d.sync += write_port.addr.eq(self.bus_i.addr - start_addr)
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m.d.sync += write_port.data.eq(self.bus_i.data)
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m.d.sync += write_port.en.eq(self.bus_i.rw)
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# Pull BRAM reads from the back of the pipeline
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with m.If(
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@ -187,7 +206,7 @@ class MemoryCore(MantaCore):
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& (self._bus_pipe[2].addr >= start_addr)
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& (self._bus_pipe[2].addr <= stop_addr)
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):
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m.d.sync += self.bus_source.p.data.eq(read_port.data)
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m.d.sync += self.bus_o.data.eq(read_port.data)
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def _tie_mems_to_user_logic(self, m):
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# Handle write ports
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@ -218,12 +237,12 @@ class MemoryCore(MantaCore):
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# Pipeline the bus to accommodate the two clock-cycle delay in the memories
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self._bus_pipe = [Signal(InternalBusLayout, name=f"bus_pipe_{i}") for i in range(3)]
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m.d.sync += self._bus_pipe[0].eq(self.bus_sink.p)
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m.d.sync += self._bus_pipe[0].eq(self.bus_i)
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for i in range(1, 3):
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m.d.sync += self._bus_pipe[i].eq(self._bus_pipe[i - 1])
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m.d.sync += self.bus_source.p.eq(self._bus_pipe[1])
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m.d.sync += self.bus_o.eq(self._bus_pipe[1])
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self._tie_mems_to_bus(m)
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self._tie_mems_to_user_logic(m)
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@ -1,4 +1,5 @@
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from amaranth import *
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from cobs import cobs
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from serial import Serial
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from manta.ethernet.bridge import EthernetBridge
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@ -11,19 +12,12 @@ from manta.uart.transmitter import UARTTransmitter
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from manta.utils import *
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class UARTInterface(wiring.Component):
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class UARTInterface(Elaboratable):
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"""
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A synthesizable module for UART communication between a host machine and
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the FPGA.
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"""
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# Top-Level Ports
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rx: In(1)
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tx: Out(1)
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bus_source: Out(InternalBusSignature)
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bus_sink: In(InternalBusSignature)
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def __init__(self, port, baudrate, clock_freq, stall_interval=16, chunk_size=256):
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"""
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This function is the main mechanism for configuring a UART Interface
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@ -77,6 +71,16 @@ class UARTInterface(wiring.Component):
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self._stall_interval = stall_interval
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self._check_config()
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# Top-Level Ports
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self.rx = Signal()
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self.tx = Signal()
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self.bus_o = Signal(InternalBusLayout)
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self.bus_i = Signal(InternalBusLayout)
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self._seq_num = 0
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self._max_retries = 3
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@classmethod
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def from_config(cls, config):
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integer_options = [
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@ -195,10 +199,94 @@ class UARTInterface(wiring.Component):
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self._serial_device = Serial(chosen_port, self._baudrate, timeout=1)
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return self._serial_device
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def get_top_level_ports(self):
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"""
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Return the Amaranth signals that should be included as ports in the
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top-level Manta module.
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"""
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return [self.rx, self.tx]
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@property
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def clock_freq(self):
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return self._clock_freq
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def _read_request(self, addr, length):
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for _ in range(self._max_retries):
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header = EthernetMessageHeader.from_params(
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MessageTypes.READ_REQUEST, self._seq_num, length
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)
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request = bytestring_from_ints([header.as_bits(), addr], byteorder="little")
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request_encoded = cobs.encode(request) + b"\x00"
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ser = self._get_serial_device()
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ser.write(request_encoded)
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response = ser.read_until(b"\x00")
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response = cobs.decode(response[:-1]) # remove zero delimiter
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# response = [words_to_value(b[::-1], 8) for b in split_into_chunks(response, 4)]
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response = [words_to_value(b, 8) for b in split_into_chunks(response, 4)]
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header = EthernetMessageHeader.from_bits(response[0])
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read_data = response[1:]
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if header.msg_type == MessageTypes.READ_RESPONSE:
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assert len(read_data) == length
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self._seq_num += 1
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return read_data
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elif header.msg_type == MessageTypes.NACK:
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self._seq_num = header.seq_num
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else:
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raise ValueError("Unexpected message format received!")
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raise ValueError("Maximum number of retries exceeded!")
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def _write_request(self, addr, datas):
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for _ in range(self._max_retries):
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header = EthernetMessageHeader.from_params(MessageTypes.WRITE_REQUEST, self._seq_num)
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request = bytestring_from_ints([header.as_bits(), addr, *datas], byteorder="little")
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request_encoded = cobs.encode(request) + b"\x00"
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ser = self._get_serial_device()
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ser.write(request_encoded)
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response = ser.read_until(b"\x00")
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response = cobs.decode(response[:-1]) # remove zero delimiter
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response = [words_to_value(b, 8) for b in split_into_chunks(response, 4)]
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header = EthernetMessageHeader.from_bits(response[0])
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if header.msg_type == MessageTypes.WRITE_RESPONSE:
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self._seq_num += 1
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return
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elif header.msg_type == MessageTypes.NACK:
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self._seq_num = header.seq_num
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else:
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raise ValueError("Unexpected message format received!")
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raise ValueError("Maximum number of retries exceeded!")
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def read_block(self, base_addr, length):
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data = []
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offset = 0
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while offset < length:
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chunk_size = min(EthernetMessageHeader.MAX_READ_LENGTH, length - offset)
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data += self._read_request(base_addr + offset, chunk_size)
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offset += chunk_size
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assert len(data) == length
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return data
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def write_block(self, base_addr, data):
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data_chunks = split_into_chunks(data, EthernetMessageHeader.MAX_WRITE_LENGTH)
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for i, chunk in enumerate(data_chunks):
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self._write_request(base_addr + (i * EthernetMessageHeader.MAX_WRITE_LENGTH), chunk)
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def read(self, addrs):
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"""
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Read the data stored in a set of address on Manta's internal memory.
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@ -213,42 +301,14 @@ class UARTInterface(wiring.Component):
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if not all(isinstance(a, int) for a in addrs):
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raise TypeError("Read address must be an integer or list of integers.")
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# Send read requests in chunks, and read bytes after each.
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# The input buffer exposed by the OS on most hosts isn't terribly deep,
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# so sending in chunks (instead of all at once) prevents the OS's input
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# buffer from overflowing and dropping bytes, as the FPGA will send
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# responses instantly after it's received a request.
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set = self._get_serial_device()
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addr_chunks = split_into_chunks(addrs, self._chunk_size)
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data = []
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for addr_chunk in addr_chunks:
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# Encode addrs into read requests
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bytes_out = "".join([f"R{a:04X}\r\n" for a in addr_chunk])
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# Add a \n after every N packets, see:
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# https://github.com/fischermoseley/manta/issues/18
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bytes_out = split_into_chunks(bytes_out, 7 * self._stall_interval)
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bytes_out = "\n".join(bytes_out)
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set.write(bytes_out.encode("ascii"))
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# Read responses have the same length as read requests
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bytes_expected = 7 * len(addr_chunk)
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bytes_in = set.read(bytes_expected)
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if len(bytes_in) != bytes_expected:
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raise ValueError(f"Only got {len(bytes_in)} out of {bytes_expected} bytes.")
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# Split received bytes into individual responses and decode
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responses = split_into_chunks(bytes_in, 7)
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data_chunk = [self._decode_read_response(r) for r in responses]
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data += data_chunk
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seqs = parse_sequences(addrs)
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for base_addr, length in seqs:
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data += self.read_block(base_addr, length)
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return data
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def write(self, addrs, data):
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def write(self, addrs, datas):
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"""
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Write the provided data into the provided addresses in Manta's internal
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memory. Addresses and data must be specified as either integers or a
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@ -256,58 +316,24 @@ class UARTInterface(wiring.Component):
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"""
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# Handle a single integer address and data
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if isinstance(addrs, int) and isinstance(data, int):
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return self.write([addrs], [data])
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if isinstance(addrs, int) and isinstance(datas, int):
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return self.write([addrs], [datas])
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# Make sure address and data are all integers
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if not isinstance(addrs, list) or not isinstance(data, list):
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# Make sure address and datas are all integers
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if not isinstance(addrs, list) or not isinstance(datas, list):
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raise TypeError("Write addresses and data must be an integer or list of integers.")
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if not all(isinstance(a, int) for a in addrs):
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raise TypeError("Write addresses must be all be integers.")
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if not all(isinstance(d, int) for d in data):
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if not all(isinstance(d, int) for d in datas):
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raise TypeError("Write data must all be integers.")
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# Since the FPGA doesn't issue any responses to write requests, we
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# the host's input buffer isn't written to, and we don't need to
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# send the data as chunks as the to avoid overflowing the input buffer.
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# Encode addrs and data into write requests
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bytes_out = "".join([f"W{a:04X}{d:04X}\r\n" for a, d in zip(addrs, data)])
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set = self._get_serial_device()
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set.write(bytes_out.encode("ascii"))
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def _decode_read_response(self, response_bytes):
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"""
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Check that read response is formatted properly, and return the encoded
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data if so.
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"""
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# Make sure response is not empty
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if response_bytes is None:
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raise ValueError("Unable to decode read response - no bytes received.")
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# Make sure response is properly encoded
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response_ascii = response_bytes.decode("ascii")
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if len(response_ascii) != 7:
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raise ValueError("Unable to decode read response - wrong number of bytes received.")
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if response_ascii[0] != "D":
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raise ValueError("Unable to decode read response - incorrect preamble.")
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for i in range(1, 5):
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if response_ascii[i] not in "0123456789ABCDEF":
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raise ValueError("Unable to decode read response - invalid data byte.")
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if response_ascii[5] != "\r":
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raise ValueError("Unable to decode read response - incorrect EOL.")
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if response_ascii[6] != "\n":
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raise ValueError("Unable to decode read response - incorrect EOL.")
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return int(response_ascii[1:5], 16)
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seqs = parse_sequences(addrs)
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offset = 0
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for base_addr, length in seqs:
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self.write_block(base_addr, datas[offset : offset + length])
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offset += length
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def elaborate(self, platform):
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m = Module()
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@ -321,15 +347,28 @@ class UARTInterface(wiring.Component):
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m.submodules.uart_tx = uart_tx = UARTTransmitter(self._clocks_per_baud)
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m.d.comb += uart_rx.rx.eq(self.rx)
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wiring.connect(m, uart_rx.source, cobs_decode.sink)
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# Use m.d.comb instead of wiring.connect because the signatures don't match exactly
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# (cobs_decode.sink accepts a ready signal, but uart_rx.source doesn't provide one)
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m.d.comb += cobs_decode.sink.data.eq(uart_rx.source.data)
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m.d.comb += cobs_decode.sink.valid.eq(uart_rx.source.valid)
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wiring.connect(m, cobs_decode.source, stream_packer.sink)
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wiring.connect(m, stream_packer.source, bridge.sink)
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wiring.connect(m, bridge.source, stream_unpacker.sink)
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wiring.connect(m, stream_unpacker.source, cobs_encode.sink)
|
||||
wiring.connect(m, cobs_encode.source, uart_tx.sink)
|
||||
|
||||
# Use m.d.comb instead of wiring.connect because the signatures don't match exactly
|
||||
# (cobs_encode.source has a last signal, but uart_tx.sink doesn't)
|
||||
m.d.comb += uart_tx.sink.data.eq(cobs_encode.source.data)
|
||||
m.d.comb += uart_tx.sink.valid.eq(cobs_encode.source.valid)
|
||||
m.d.comb += cobs_encode.source.ready.eq(uart_tx.sink.ready)
|
||||
|
||||
m.d.comb += self.tx.eq(uart_tx.tx)
|
||||
|
||||
wiring.connect(m, bridge.bus_source, wiring.flipped(self.bus_source))
|
||||
wiring.connect(m, wiring.flipped(self.bus_sink), bridge.bus_sink)
|
||||
# Use m.d.comb instead of wiring.connect as self.bus_o and self.bus_i are just Signals,
|
||||
# not Signatures.
|
||||
m.d.comb += self.bus_o.eq(bridge.bus_source.p)
|
||||
m.d.comb += bridge.bus_sink.p.eq(self.bus_i)
|
||||
|
||||
return m
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ from amaranth.lib.wiring import In, Out
|
|||
from amaranth.sim import Simulator
|
||||
|
||||
|
||||
class MantaCore(ABC, wiring.Component):
|
||||
class MantaCore(ABC, Elaboratable):
|
||||
# These attributes are meant to be settable and gettable, but max_addr and
|
||||
# top_level_ports are intended to be only gettable. Do not implement
|
||||
# setters for them in subclasses.
|
||||
|
|
@ -29,6 +29,15 @@ class MantaCore(ABC, wiring.Component):
|
|||
"""
|
||||
pass
|
||||
|
||||
@property
|
||||
@abstractmethod
|
||||
def top_level_ports(self):
|
||||
"""
|
||||
Return the Amaranth signals that should be included as ports in the
|
||||
top-level Manta module.
|
||||
"""
|
||||
pass
|
||||
|
||||
@abstractmethod
|
||||
def to_config(self):
|
||||
"""
|
||||
|
|
|
|||
Loading…
Reference in New Issue