From 165c6e46cae35846148371d0ce69f3de9b3cf7ed Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Thu, 1 Aug 2024 07:26:55 -0700 Subject: [PATCH] tests: fix logic_analyzer_sim --- test/test_logic_analyzer_sim.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/test/test_logic_analyzer_sim.py b/test/test_logic_analyzer_sim.py index 85b4cf6..b84d978 100644 --- a/test/test_logic_analyzer_sim.py +++ b/test/test_logic_analyzer_sim.py @@ -10,6 +10,7 @@ moe = Signal(9) la = LogicAnalyzerCore(1024, [larry, curly, moe]) la.base_addr = 0 +_ = la.max_addr async def print_data_at_addr(ctx, addr): @@ -33,7 +34,7 @@ async def print_data_at_addr(ctx, addr): async def set_fsm_register(ctx, name, data): addr = la._fsm.registers._memory_map[name]["addrs"][0] - strobe_addr = la._fsm.registers._base_addr + strobe_addr = la._fsm.registers.base_addr await write_register(la, ctx, strobe_addr, 0) await write_register(la, ctx, addr, data) @@ -43,7 +44,7 @@ async def set_fsm_register(ctx, name, data): async def set_trig_blk_register(ctx, name, data): addr = la._trig_blk.registers._memory_map[name]["addrs"][0] - strobe_addr = la._trig_blk.registers._base_addr + strobe_addr = la._trig_blk.registers.base_addr await write_register(la, ctx, strobe_addr, 0) await write_register(la, ctx, addr, data)