58 lines
1.4 KiB
Python
58 lines
1.4 KiB
Python
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from amaranth.sim import Simulator
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from manta.uart import UARTTransmitter
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from manta.utils import *
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from random import sample
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uart_tx = UARTTransmitter(clocks_per_baud=10)
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def verify_bit_sequence(byte):
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"""
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Request a byte to be transmitted, and verify that the sequence of bits is correct.
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"""
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# Request byte to be transmitted
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yield uart_tx.data_i.eq(byte)
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yield uart_tx.start_i.eq(1)
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yield
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yield uart_tx.data_i.eq(0)
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yield uart_tx.start_i.eq(0)
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yield
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# Check that data bit is correct on every clock baud period
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# 8N1 serial, LSB sent first
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data_bits = "0" + f"{byte:08b}"[::-1] + "1"
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data_bits = [int(bit) for bit in data_bits]
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for i in range(10 * uart_tx.clocks_per_baud):
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bit_index = i // uart_tx.clocks_per_baud
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if (yield uart_tx.tx) != data_bits[bit_index]:
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raise ValueError("Wrong bit in sequence!")
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if (yield uart_tx.done_o) and (bit_index != 9):
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raise ValueError("Done asserted too early!")
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yield
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if not (yield uart_tx.done_o):
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raise ValueError("Done not asserted at end of transmission!")
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def test_all_possible_bytes():
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def testbench():
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for i in range(0xFF):
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yield from verify_bit_sequence(i)
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simulate(uart_tx, testbench)
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def test_bytes_random_sample():
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def testbench():
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for i in sample(range(0xFF), k=0xFF):
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yield from verify_bit_sequence(i)
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simulate(uart_tx, testbench)
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