manta/examples/verilog/nexys4_ddr/uart_logic_analyzer/manta.yaml

19 lines
264 B
YAML
Raw Normal View History

---
cores:
my_logic_analyzer:
type: logic_analyzer
sample_depth: 256
probes:
probe0: 1
probe1: 4
probe2: 8
probe3: 16
triggers:
- probe2 EQ 3
uart:
port: "/dev/ttyUSB1"
baudrate: 115200
clock_freq: 100000000