tech files which incorrectly parses the syntax using five
parameters. This syntax variant does not get used often, which
is why the error went undetected for a long time.
run free() on a memory location that was never allocated. This
error has no effect on anything, but correcting it prevents magic
from issuing a mysterious warning.
caused by other code that can move the plane of a device to match
the plane of a port. Solved by retaining the original plane of the
node in the extTransRec structure, and using that to determine the
device plane for purposes of calculating perimeters and not double-
counting contacts.
fringe capacitance halo where the default halo distance was set to
zero instead of one and caused divide-by-zero issues; (2) Found
extraction issues where labels picked up from cells flattened
during GDS reading cause the flattened/emptied cells to show up
in the extraction with extra pins that can mess up LVS. Solved
this by removing labels from flattened/emptied cells.
using the newer methods for nearest-edge searching and fringe area
of effect. Removed a same-net check in a routine that removes
capacitances that are redundant due to hierarchical overlaps; these
redundancies must be checked on shapes within the same net. Corrected
(again) an out-of-clip-bounds check.
reading GDS files, caused by an unneeded change to pass both
the "original" filename and the actual filename when handling
compressed files---The original filename is unneeded.
(2) Implemented several new methods for parasitic extraction. The
first is an option offset value to apply to sidewall calculations.
This handles issues where actual wire separation is different
from drawn wire separation, which can be significant for the
1/d calculation of sidewall coupling. The second method is to
use the recently-added fringe halo to compute the coupling of the
fringe capacitance to nearby wires. Prior to this change, all
fringe capacitance was applied to surfaces directly under a wire
edge as if the fringe capacitance did not extend outward from the
edge. Now the capacitance is properly pro-rated for the position
of any overlapped shape inside the fringing field. Finally, the
third method added is a new search algorithm for finding the
nearest shapes along the length of a boundary. This is used for
sidewall coupling and fringe shielding, where the nearest shape
dominates the coupling, and any shapes behind are shielded and
may (to first order) be ignored. Previously, the entire halo
was searched without regard to shapes shielding other shapes
behind, and a recent correction added an ad-hoc search for
blocking shapes that was inefficient and not always correct.
The new method is both efficient and accurate.
to the fringe shielding calculations, which uses very similar code and
suffered the same problem of not being able to recognize when another
shape was between the two edges under consideration. Fixing this
makes the fringe shielding calculations symmetric, as they should be.
computing coupling to shapes that are shielded by other
intervening shapes. This is not a perfect solution but will
properly handle all but a few pathological cases.
which instead of defining a device or subcircuit that exists inside
the cell, instead redefines the cell itself as a device or subcircuit
model that exists in the PDK. This is used where a specific layout
subcell has its own associated device definition in the PDK. Instead
of the "device" property value being the line that gets generated for
a device in the subcells .ext file, the property value should be the
word "primitive" optionally followed by any parameters that need to
be passed to the subcircuit call.
recognized as a valid command when file locking has been disabled as
a compile-time option. The command then generates an error on
"locking enable" but simply ignores the command "locking disable".
substrate shielding types in a subcell inside the interaction area
only. Since the interaction area is clipped by the "cookie cutter"
extraction areas, it could completely miss the shielding. As
revised, any shielding under a subcell will effectively shield the
entire subcell. This could be improved by warning if the subcell
has substrate connections outside of the shield area (as that is
not extractable), but that requires additional processing.
fact that "extract all" does not enumerate cells from bottom up
as I had assumed---The order is roughly bottom-to-top, but cells
re-used in different places in the hierarchy could end up called
before one or more of their own subcells is extracted. Since
this conflicted with the preparation of the substrate in each
extracted subcircuit, I changed the method to enumerate cells so
that it is properly bottom-to-top. Also, methods were added to
"extract" (incremental), "extract cell", and "extract parents"
to ensure that the substrate is prepared on all subcells before
extraction.
extFindNodes() does; consequently, ExtLabelRegions() when called
after ExtFindRegions() may accidentally chain together a substrate
region with whatever was left in this linked list after the
previous call to extFindNodes(), with unpredictable results.
is specified in the extraction section of the techfile, then magic
will compute the effect of a nearby shape partially shielding the
sidewall overlap capacitance, which approaches 100% shielding as
the shapes converge to zero separation. This method prevents
magic from vastly overestimating the fringe capacitance of closely
spaced wires, which was magic's worst problem with parasitic
accuracy. The "fringeshieldhalo" value is the distance at which
the fringe shielding becomes negligible. Typically, it will be
about three times the distance at which half the fringe value is
shielded. It may be necessary at some point to make both the
fringe shielding halo and the sidewall halo values per-type values
(or per-plane, at least). For now, it should suffice to bring
Magic's parasitic extraction back in line with other tools.
not be seen during hierarchical processing, causing the substrate
to get split into several names that may conflict in the netlist.
At issue is the fact that ExtLabelRegions() will not attach a
default substrate label to a default substrate region. This may
need further untangling, as extFindNodes() will set the default
substrate node and is sometimes followed by ExtLabelRegions(),
which will label it. Any place ExtFindRegions() is called, this
could be an issue.
Most of this had to do with the incorrect use of the parent's substrate
name in extHierSubstrate(). After the correction, there still remains
an issue that is caused when a labeled isolated substrate region overlaps
an extraction tile boundary. I believe that this particular error has
existed for some time and is not new, so I am committing these changes.
which had become fouled up due to the changes in the way that the
substrate is defined and handled. Worked through a large torture
test until all types of substrate coupling and overlap shielding
were resolved to be extracted as expected.
a routine that should have been called with a NULL argument, but
instead was called with no argument, making the behavior system-
dependent. Revised the parsing of the "defaultareacap" and
"defaultperimeter" statements in the tech file, such that the short
version of both statements gets automatic handling of the substrate
and isolated substrate areas; this goes back to the recent change
in extraction behavior to redefine the "substrate type" (e.g., pwell)
during extraction as defining isolated substrate areas, and not the
default substrate. The earlier code change dealt with problems
related to extracting nodes and regions, but did not consider how
parasitic capacitance was affected. This commit resolves that issue.
The extSubtree() routine cuts a layout into squares and extracts
each separately, checking for subcell interactions. In each
square it parses all labels looking for unconnected ones. This
section of code not only parses all labels M x N times, but it
then marks interaction areas where there may be none, forcing
additional unnecessary processing. This commit makes the first
quick optimization, which is to change the return value of
DRCFindInteractions() from boolean to integer, allowing it to
return a value indicating that there are no subcells in the
area. This prevents the loop through labels from happening in
cases where there can never be interactions. More to come.
effectively forcing the substrate type (e.g., "pwell") to be defined
as delineating isolated substrate areas only (e.g., pwell in deep nwell
or isosub a.k.a. subcut). It does so by erasing all of the substrate
type out of a cell prior to extraction before redrawing it in the
isolated areas. This avoids issues caused by pwell drawn in separate
unconnected areas of a cell, as these are removed and the area treated
as the default substrate everywhere. Has worked on all layouts tested
so far.
check for abstract views to determine how to handle the substrate
node. Running tests to check if this has any negative impact on
the extraction of abstract views that do not specify substrate
and well types.
traditionally been kept for backwards compatibility. However, the
operation of "ext2spice" and "ext2sim" as separate programs has
become extremely difficult to maintain, and so it has been dropped
in favor of folding both into the program as commands, as was done
a long time ago in the Tcl/Tk version.
the timestamp is updated after reading in CIF or GDS, and managed to
get the timestamp dirty flag to remain clear after reading when
"gds datestamp" is used. This includes a modification of the timestamp
update routine that only updates timestamps on a single file if only a
single file is being written.
file to generate a mask of all the types called out in the section
as being used for parasitic calculations (resistive and capacitive)
and device terminal types. This is supplemented with a list of all
types that are specified in the "connect" and "contact" sections as
connecting to something other than themselves. All remaining types
are considered non-electrical and removed from the list of types
that can be considered electrical nodes. This works a bit better
than the existing method of using "resist <types> None" to specify
non-electrical types, as it is backwardly-compatible to older tech
files. The upshot is that in the worst case, if a type needs to be
extracted as an electrical node but does not satisfy any of the
above criteria, then it should be added to the "resist" list, with
a resistance of 0 if necessary.
time ago by cleaning up excess usage of "equiv" lines in the .ext
file output. The hierarchical extraction code did not distinguish
between node names which were output and those that were not,
requiring a setting "extract do aliases" to force all node aliases
to be output with "equiv" statements. So hierarchical names
might be any alias, whether output or not, and "merge" and "cap"
lines might contain references to nodes that were not output,
causing them to be disconnected nodes. This fix handles the
"extract no aliases" (default) case by flagging node names that
are redundant and not output, and not creating hierarchical names
with them.
node representing the global substrate on cells that are abstract
views. Corrected a typecasting issue in ext2spice.c that throws
a compiler warning. Added another check for a cell being editable
when painting, which is a case that was not covered by the
previous code change to address the same issue.
Print the names of the tile types that are illegally overlapping. This
gives us a better idea of what is wrong, eg:
feedback add "Illegal overlap between obsm2 and m2 (types do not connect)" medium
"defaultareacap" and "defaultperimeter" statements in the technology
file. Now, the parser makes use of the configuration of the
substrate from the "substrate" line to generate a default list of
which types and planes represent the substrate, and which types and
planes represent shielding to the substrate. This solves an issue
with the use of substrate isolation layers (e.g., "isosub" in
sky130A), because its definition and usage created substrate shields
on two planes (well and dwell), while the syntax for "defaultareacap"
and "defaultperimeter" only allow one shielding plane to be defined.
value 1 after finding a substrate connecting type shielded (by deep
nwell, in the example) from the substrate, thus preventing the
search from processing any remaining substrate types. Solved by
changing the return value to zero to keep the search going.
record to the label structure to hold the port number. One major
issue stemming from this was reported in github issue #203 by Anton
Blanchard. This commit fixes that error.
clean up memory after running "ext2spice". There are apparently
still memory leaks somewhere, difficult to diagnose with valgrind,
but this fix removes the most substantial leakage and allows
"ext2spice" to be run continuously, at least for a while.
this limited ports to 16384, which seemed reasonable at the time.
However, the sky130_sram_macro layouts connect power and ground in a
way that when coupled with "extract unique" can generate tens of
thousands of ports and overrun the bit field, showing that automation
can do the unexpected. The solution was to split out the port number
from the label record as its own 32-bit value.
connections through the substrate as the same node, and so will
not force different nodes names on the soft connection to be
unique. This should probably be selectable behavior. However, as
written, the "extract" command will always merge soft connections,
so giving them unique names just causes problems with "extract".
entries for "floating" labels. Otherwise it is possible for the
hierarchical checks to find the label in flattened geometry and
reference it, resulting in merge statements in an .ext file that
reference undeclared nodes, ultimately resulting in extflat
failing to perform the merge, and an incorrect netlist.
Tim Edwards
Anton Blanchard