Commit Graph

327 Commits

Author SHA1 Message Date
Tim Edwards 4201980923 Update at Fri Dec 28 10:29:29 EST 2018 by tim 2018-12-28 10:29:29 -05:00
Tim Edwards 34ae6ea9cc Corrected error in technology file reloading that causes the plow
module to fill up its rules table and start printing errors about
the table overflow.  Tables are now properly reset on tech reload.
2018-12-14 16:33:34 -05:00
Tim Edwards 53fd26d1bc Corrected DRC "why" message subsitution sequence "%a" so that it
corresponds to drcc_cdist, which encodes the area (not drcc_dist).
2018-12-14 14:02:54 -05:00
Tim Edwards 880ebde614 Merge branch 'work' into tomerge 2018-12-14 11:58:25 -05:00
Tim Edwards 213749d009 Update at Fri Dec 14 11:58:22 EST 2018 by tim 2018-12-14 11:58:22 -05:00
Tim Edwards 6aa0895e6f Created a method for distance substitutions in DRC "why" strings in
DRC rules.  The substitutions are specified by "%d" for the main
rule distance, "%c" for the corner rule distance (sometimes
interpreted differently;  e.g., as width in the widespacing rule),
and "%a" for rule area (e.g., maxarea rule).  In addition to
simplifying the process of writing rule violation strings, the
benefits are twofold:  (1) The output is in meaningful physical
units, but in the case of SCMOS technology, will scale properly
depending on the selected GDS output style, and in the case of
all technologies, will scale properly with internal grid division;
and (2) when using lambda, but where rules are given in vendor
minimum dimensions, the rules will be based on the lambda rule
approximation (that is, distances will be rounded to the nearest
lambda but reported in microns).  Behavior is unchanged from
previous versions for "why" strings not using the defined
substitution sequences.
2018-12-14 11:51:27 -05:00
Tim Edwards 533017c8c7 Merge branch 'work' into tomerge 2018-12-13 12:05:18 -05:00
Tim Edwards bd583f476b Update at Thu Dec 13 12:05:16 EST 2018 by tim 2018-12-13 12:05:16 -05:00
Tim Edwards f3d191981d Corrected a few aspects of LEF write: (1) Put BUSBITCHARS in the
header, (2) Use CLASS BLOCK in the macro if no class is defined,
and (3) Add END LIBRARY to the end of the file.
2018-12-13 12:04:10 -05:00
Tim Edwards 3bfc2bd620 Merge branch 'work' into tomerge 2018-12-12 17:25:17 -05:00
Tim Edwards 3fa8a88a79 Update at Wed Dec 12 17:25:15 EST 2018 by tim 2018-12-12 17:25:15 -05:00
Tim Edwards f3a95c74fe Corrected hierarchical SPICE extraction to reset the subcircuit
name-to-number mapping used for the HSPICE format between
subcircuits.  Otherwise, subcircuits with the same instance ID
remain in the table and may cause nodes to be output with a name
that collides with other names in the same subcircuit.  This only
affects output in HSPICE format.
2018-12-12 17:23:35 -05:00
Tim Edwards fc0645a88e Merge branch 'work' into tomerge 2018-12-07 10:12:31 -05:00
Tim Edwards a746acea5c Update at Fri Dec 7 10:12:29 EST 2018 by tim 2018-12-07 10:12:29 -05:00
Tim Edwards 4da51bc42a Modified the "makedbh" script to avoid intermixing "printf" and
"echo", because there is at least one OS variant out there where
the two buffer independently and cause the output to have lines
out of order.  The script had previously used "printf" because
"echo -n" is not POSIX-compliant and so not necessarily universally
compatible.  The script was changed to use "printf" throughout.
2018-12-07 10:10:22 -05:00
Tim Edwards ba9dfb7765 Merge branch 'work' into tomerge 2018-11-20 13:07:56 -05:00
Tim Edwards 5802fab980 Update at Tue Nov 20 13:07:54 EST 2018 by tim 2018-11-20 13:07:54 -05:00
Tim Edwards 5804bd3326 Minor typo correction. 2018-11-20 13:04:44 -05:00
Tim Edwards 5e28e84336 Merge branch 'work' into tomerge 2018-11-19 15:04:32 -05:00
Tim Edwards f30f976bc7 Update at Mon Nov 19 15:04:29 EST 2018 by tim 2018-11-19 15:04:29 -05:00
Tim Edwards 17227ee427 Added new option "-hide" to the "lef write" command, which causes
the output to have an obstruction area over the entire cell except
for a keep-out area around each pin.  Instead of marking every
part of the pin geometry, only the "chunk" (largest immediate
rectangle) surrounding the port label is output as part of port
LEF geometry.  This avoids making unnecessarily complicated
abstract views, and makes it easier for other tools to read and
manage the same abstract views.
2018-11-19 15:01:20 -05:00
Tim Edwards f756825828 Removed a few diagnostic output statements from the last commit. 2018-11-16 14:43:41 -05:00
Tim Edwards ee6834abde Merge branch 'work' into tomerge 2018-11-16 14:04:00 -05:00
Tim Edwards 852dabeee1 Update at Fri Nov 16 14:03:58 EST 2018 by tim 2018-11-16 14:03:58 -05:00
Tim Edwards dd3a92762c Update for writing files from abstract views. Previous behavior was
to prefix all library components read from GDS files pointed to by
an abstract view (other than the cell itself) with a prefix.  But
this does not account for the fact that the same library may be read
by other cells.  The solution is for every cell in the library, check
if there is a cell in magic with the same name which is also an abstract
view that points to the same GDS library.  Those cells do not get
prefixes.  At the same time, however, it was discovered that the GDS
cellname character limit is set at 32, and so prefixes must be kept
short.  To keep the prefixes unique, the prefix was changed to a 4
character random alphanumeric sequence, and a warning is issued if
any GDS cell exceeds the 32 character limit.
2018-11-16 13:59:17 -05:00
Tim Edwards eca3ba25b3 Merge branch 'work' into tomerge 2018-11-15 15:57:58 -05:00
Tim Edwards a2ef591c8d Update at Thu Nov 15 15:57:56 EST 2018 by tim 2018-11-15 15:57:56 -05:00
Tim Edwards 395fb1a8d6 Corrected node merging, which failed to copy the EF_TOP_PORT flag
bit into the merged node.  Corrected reference to efNodeHashTable
to the more proper call to EFHNLook().
2018-11-15 15:55:41 -05:00
Tim Edwards cf9f9784ed Merge branch 'work' into tomerge 2018-11-12 13:27:15 -05:00
Tim Edwards 131ac3156f Update at Mon Nov 12 13:27:12 EST 2018 by tim 2018-11-12 13:27:12 -05:00
Tim Edwards 66603cdb53 Corrected invalid logic in the interpetation of (cif/gds) label
options "text", "port", and "noport" in the techfile.  The
incorrect interpretation was preventing backwards compatibility,
such that ports would not be output on GDS layers if the "port"
option was not used.
2018-11-12 13:25:05 -05:00
Tim Edwards 648b9e54e6 Corrected "ext2spice lvs" to add "global off" as a setting, which
is normal for top level designs (no implicit label connections
should be made at the top level).
2018-10-31 15:41:22 -04:00
Tim Edwards 56e838ebb6 Merge branch 'work' into tomerge 2018-10-31 14:36:02 -04:00
Tim Edwards 27697d36cc Update at Wed Oct 31 14:36:01 EDT 2018 by tim 2018-10-31 14:36:01 -04:00
Tim Edwards 6f8ec21a11 Two improvements: (1) Command extension "ext2spice lvs" sets up
all the settings normally used for LVS (hierarchy on, cthresh
infinite, subcircuit top auto, etc.).  (2) Extract and extract
unique ignore cells marked as abstract views (property LEFview
is set) when checking for unconnected nets with the same name
label.
2018-10-31 14:33:24 -04:00
Tim Edwards fa17436fef Corrected a few errors in the implementation of "csubcircuit",
now fully tested and verified.
2018-10-30 21:56:05 -04:00
Tim Edwards e20319f3c1 Corrected an error in the last commit that causes serious problems
in the SPICE netlist when using new device "csubcircuit" due to
a mismatch in the expected number of parameters.  However, more
work needs to be done to cover capacitor top and bottom plates on
different planes.
2018-10-30 17:17:49 -04:00
Tim Edwards a36b12eadd Merge branch 'work' into tomerge 2018-10-30 16:22:12 -04:00
Tim Edwards 67c69346da Update at Tue Oct 30 16:22:11 EDT 2018 by tim 2018-10-30 16:22:11 -04:00
Tim Edwards 7dc15a7d28 Added extraction device type "csubcircuit", which should have been
added a long time ago, since capacitors use a different method for
calculating width and length than either transistors or resistors,
so subcircuits need a special class designator or else the extraction
may calculate the wrong dimensions for device width by totalling the
perimeter between the device and terminal types, as it would for a
MOSFET.
2018-10-30 16:19:20 -04:00
Tim Edwards 0944b02f5f Merge branch 'work' into tomerge 2018-10-29 17:32:09 -04:00
Tim Edwards e51991b0f1 Update at Mon Oct 29 17:32:07 EDT 2018 by tim 2018-10-29 17:32:07 -04:00
Tim Edwards 79a3934d40 Corrected an error that was previously assumed to be fixed in
8.2.74.  Top-level port names are now flagged independently of
any subcircuit port, so they are easier to identify when determining
naming precedence for the net.  This makes the code cleaner and
removes the problems arising from non-top-level ports and global
names overriding the subcircuit port names.
2018-10-29 17:29:15 -04:00
Tim Edwards a126a3fe74 Merge branch 'work' into tomerge 2018-10-23 08:49:17 -04:00
Tim Edwards 16a0923085 Update at Tue Oct 23 08:49:15 EDT 2018 by tim 2018-10-23 08:49:15 -04:00
Tim Edwards bb0af34441 Corrected an obscure error that causes the background of the layout
window to change after hiding a layer using the toolbar and then
refreshing the layout.  Fixed by saving and restoring the graphics
state around the routine that configures the toolbar image.  Also
added a check to CifPaintCurrent to guard against using an unassigned
ClientData record as a pointer (causes a crash), and added braces
around "expr" values in the Tcl wrapper, which reportedly results in
faster execution of the expression.
2018-10-23 08:44:04 -04:00
Tim Edwards 08e0e9aab4 Merge branch 'work' into tomerge 2018-10-17 10:33:40 -04:00
Tim Edwards 9171bfddf4 Update at Wed Oct 17 10:33:38 EDT 2018 by tim 2018-10-17 10:33:38 -04:00
Tim Edwards 2914286921 Resolved a tricky issue with the crosshair drawing. The crosshair
routine was erasing and redrawing in one step, which ignored the
possibility of having to erase from one window and redraw in
another if the cursor moved focus from one window to another.
This led to crosshairs being improperly drawn and erased when
multiple windows were present, if the windows had different cells
loaded.
2018-10-17 10:30:55 -04:00
Tim Edwards 6f841f1ff8 Merge branch 'work' into tomerge 2018-09-27 08:16:08 -04:00