EFbuild.c:466:9: warning: suggest parentheses around assignment used as truth value
EFbuild.c:662:20: warning: suggest parentheses around assignment used as truth value
EFbuild.c:682:24: warning: suggest parentheses around assignment used as truth value
EFbuild.c:690:24: warning: suggest parentheses around assignment used as truth value
EFbuild.c:1760:12: warning: suggest parentheses around assignment used as truth value
EFbuild.c:1973:9: warning: suggest parentheses around assignment used as truth value
EFbuild.c:2062:12: warning: suggest parentheses around assignment used as truth value
EFbuild.c:2063:13: warning: suggest parentheses around assignment used as truth value
EFbuild.c:2091:12: warning: suggest parentheses around assignment used as truth value
EFbuild.c:2134:12: warning: suggest parentheses around assignment used as truth value
EFbuild.c:2135:13: warning: suggest parentheses around assignment used as truth value
EFread.c:673:12: warning: suggest parentheses around assignment used as truth value
ExtArray.c:693:12: warning: suggest parentheses around assignment used as truth value
ExtArray.c:800:13: warning: suggest parentheses around assignment used as truth value
ExtBasic.c:4569:9: warning: suggest parentheses around assignment used as truth value
ExtBasic.c:4949:13: warning: suggest parentheses around assignment used as truth value
ExtBasic.c:5032:12: warning: suggest parentheses around assignment used as truth value
ExtCell.c:218:13: warning: suggest parentheses around assignment used as truth value
ExtCouple.c:222:12: warning: suggest parentheses around assignment used as truth value
ExtCouple.c:278:12: warning: suggest parentheses around assignment used as truth value
ExtCouple.c:467:9: warning: suggest parentheses around assignment used as truth value
ExtHard.c:379:12: warning: suggest parentheses around assignment used as truth value
ExtHard.c:458:12: warning: suggest parentheses around assignment used as truth value
ExtHier.c:740:16: warning: suggest parentheses around assignment used as truth value
ExtHier.c:831:12: warning: suggest parentheses around assignment used as truth value
ExtHier.c:841:13: warning: suggest parentheses around assignment used as truth value
ExtHier.c:851:17: warning: suggest parentheses around assignment used as truth value
ExtHier.c:865:34: warning: suggest parentheses around assignment used as truth value
ExtLength.c:264:12: warning: suggest parentheses around assignment used as truth value
ExtLength.c:276:12: warning: suggest parentheses around assignment used as truth value
ExtLength.c:878:9: warning: suggest parentheses around assignment used as truth value
ExtMain.c:499:12: warning: suggest parentheses around assignment used as truth value
ExtMain.c:970:12: warning: suggest parentheses around assignment used as truth value
ExtNghbors.c:298:13: warning: suggest parentheses around assignment used as truth value
ExtSubtree.c:683:12: warning: suggest parentheses around assignment used as truth value
ExtTest.c:457:21: warning: suggest parentheses around assignment used as truth value
ExtTest.c:466:21: warning: suggest parentheses around assignment used as truth value
ExtTimes.c:216:12: warning: suggest parentheses around assignment used as truth value
ExtTimes.c:226:12: warning: suggest parentheses around assignment used as truth value
ExtTimes.c:235:12: warning: suggest parentheses around assignment used as truth value
ExtYank.c:236:34: warning: suggest parentheses around assignment used as truth value
ExtYank.c:238:42: warning: suggest parentheses around assignment used as truth value
GCC14 -Wall cleanup series [-Wparentheses]
".res.ext" file from "extresist" after using "extract do local" (and
probably with "extract path" as well). Fixed this, and also made
sure that "extresist" writes the ".res.ext" file to the same location
as ".ext" always, so that handling is consistent throughout the
full R-C extraction process, across the use of "extract", "ext2sim",
"extresist", and "ext2spice".
warning messages about ports being electrically connected when
those ports have names that match under rules of case-insensitivity,
and the .ext file is being read for the purpose of generating a
SPICE netlist, which is case-insensitive. Also: Corrected a crash
condition when using "extract path <name>" when directory <name>
does not exist.
the assumption of case insensitivity (e.g., VSS, Vss, and vss)
are kept separate even when writing SPICE netlists, which are
case insensitive. The code fix both avoids flagging these ports
when running ext2spice, and more importantly, allows the use of
"ext2spice short" without these ports ending up separate in the
output netlist.
with "extract do local" now being equivalent to "extract path .".
This allows extraction files to be put in a subdirectory and not
clog up the current working directory. Also: Fixed some behavior
around the use of "ext2spice -p <path>" so that it (1) works, and
(2) is compatible with the new "extract path". Since the ext2spice
and ext2sim commands are effectively independent of the primary
extraction, the "-p" option is needed to correspond to the use of
"extract path". Hopefully this is seen as only a minor inconvenience.
can result in negative resistors due to integer overflow. In all
cases, the target was floating-point and it was only necessary to
recast everything to float first.
This commit makes the code (mostly) C99-compatible, enabling to compile
it without the -Wno-error=implicit-function-declaration flag. This
way, Magic becomes usable on arm64 architectures, specifically on Apple
computers with M1/M2 SoC.
which instead of defining a device or subcircuit that exists inside
the cell, instead redefines the cell itself as a device or subcircuit
model that exists in the PDK. This is used where a specific layout
subcell has its own associated device definition in the PDK. Instead
of the "device" property value being the line that gets generated for
a device in the subcells .ext file, the property value should be the
word "primitive" optionally followed by any parameters that need to
be passed to the subcircuit call.
substrate (bulk terminal) and global substrate. Otherwise, the
routine in ext2hier.c that finds the substrate node will find the
first device bulk connection, not the default substrate.
implements a method for handling ports in a subcircuit that have different
port names and indexes but are shorted together. "none" is the default
and backwards-compatible behavior that merges ports together, which will
often cause one of the ports to be optimized out of the netlist. "resistor"
will separate the port names with a 0-ohm ideal resistor. "voltage" will
separate the port names with a 0-volt voltage source. This should work
well for simulation and potentially for LVS, although its impact on LVS
has not been fully investigated.
could cause serious errors on systems that do not auto-zero allocated
memory. Also: Fixed an error introduced by a recent commit to allocate
character memory for efReadLine() which frees the memory before reading
a .res.ext file, causing a crash when using "ext2spice" with the
"extresist on" option.
memory for the input line instead of using a fixed 1024-character
buffer. That avoids the issue of rare but possible overflow when
reading a .ext file with unknown line lengths.
a truncated line. There is still a question as to why an example
occurred that caused a line to be truncated, and whether a buffer
size needs to be made larger or made dynamically allocated.
argument as a pointer but also set the same variable to the
return value. This is ambiguous, because the behavior depends on
whether the value being set upon return is the original value or
the reallocated value. The result is system-dependent behavior.
views. Because the abstract view does not necessarily represent
actual connectivity, rely on the port indexes in the .ext file
to determine the number of ports and port order. Do not use
SpiceNodeName() to look up the node name, or unique ports that
are deemed shorted will go missing. Also: Modified the read-in
of .ext files so that use names may contain backslashes. Only
backslashes that end a line will be handled differently.
the right argument type (float, not int). Otherwise all resistances
from extresist come out zero when doing "ext2spice extresist on"
and "ext2spice hierarchy on". Also changed the format of the resistance
in the SPICE output to type float, since values are in standard units of
ohms, and rounding to the nearest ohm seems excessively coarse-grained.
a long-standing error (introduced with the "extresist geometry"
option) that can cause nets not to be extracted (due to the first
record not having extraction data, which was itself a long-standing
error in the code but which was not fixed correctly); (2) handle
"device mosfet" type transistors (previously only handled the old
"fet" type extraction devices); and (3) correct for the res.ext
file having a different scalefactor relative to the .ext file. The
latter item was solved by forcing all input to scale like
ExtCurStyle->exts_unitsPerLambda, locally correcting all input as
needed. Note that extresist still needs to handle other extraction
devices (e.g., resistors and capacitors) but those will require
additional handling in the routines which analyze the current path
to determine how to break up wires into paths.
with ext2spice without the hierarchy option. More work needed to
produce correct hierarchical output and to support extraction
devices other than the old "fet" record.
simple FET device in extresist. Also: Extended the bloat-all CIF operator
again, allowing the trigger layer for the bloat operation to include both
CIF layers and magic layers (previously only magic layers were supported).
This extension is possible due to the previous extension allowing the
trigger layer and bloating layers to be on separate planes. This operator
extension is useful for tagging geometry that is in the proximity of, but
not overlapping, geometry on another plane.
64 because I overran the 64 array with too many resistclasses in
a techfile. This really should be dynamically allocated; this
requires parsing the line to count tokens and reallocating as
needed (to be done).
a scaling issue in extract) which was caused by the addition of
hierarchical netlist generation. Finding hierarchical connections
requires finding instances by name, so it is vastly better to create a
hash table of instances instead of a linked list.
added a long time ago, since capacitors use a different method for
calculating width and length than either transistors or resistors,
so subcircuits need a special class designator or else the extraction
may calculate the wrong dimensions for device width by totalling the
perimeter between the device and terminal types, as it would for a
MOSFET.
8.2.74. Top-level port names are now flagged independently of
any subcircuit port, so they are easier to identify when determining
naming precedence for the net. This makes the code cleaner and
removes the problems arising from non-top-level ports and global
names overriding the subcircuit port names.
symmetric with writing them. Since the writing of .ext files
was changed to preferably use the location of the cell being
read, and since the extflat database does not save this path
information, it was necessary to check the main database entry
for each cell to determine if there is a non-default path where
the .ext file may have been saved (with the current working
directory used as a fall-back if the directory is not writeable).
development had been halted since it was first created back in April.
Version 8.2 is now the official development version, with the first
development push to create a Cairo graphics interface.
Darryl L. Miles
Tim Edwards
Alessandro De Laurenzis
Anton Blanchard