"csubcircuit" but swaps the first two pins (with the device
identifier layer becoming the 2nd pin and the other terminal the
first), which is needed for n-type diodes modeled as subcircuits
where the subcircuit pin order matches the order of pins for a
SPICE n-type diode component. Previously "msubcircuit" was used
for this purpose, but will calculate the wrong L and W. While
use of L and W for diodes is rare, this device type also works for
reversed capacitors (where the bottom or non-identifying layer
terminal is in the first pin position of the subcircuit).
version 8.3.521 that, due to an argument size mismatch, causes
device parameters in netlist output to be printed as zero.
Also added a small extension to the list of extraction types
to include "device veriloga", which has the same syntax as
"device subcircuit" but generates a component type "N"
(Verilog-A component) in the netlist output.
Additionally the HierName's hierName1 and hierName2 arguments have been
made 'const' to help convey the receiver can not modify the referenced
data passed.
This has a knock on effect of causing EFvisit.c to require database.h
to be defined BEFORE the EFint.h due to an identical copy of ArrayInfo
type being present in both files.
Maybe there should be database_arrayinfo.h ? To remove the copy.
I think the warning is bringing to attention the hidden fall-thru
case situation.
EFvisit.c:897:50: warning: misleading indentation; statement is not part of the previous 'if'
clang18 -Wall warning cleanup [-Wmisleading-indentation]
EFdef.c:110:12: warning: suggest parentheses around assignment used as truth value
EFdef.c:154:12: warning: suggest parentheses around assignment used as truth value
EFdef.c:167:12: warning: suggest parentheses around assignment used as truth value
EFflat.c:546:17: warning: suggest parentheses around assignment used as truth value
EFflat.c:798:12: warning: suggest parentheses around assignment used as truth value
EFflat.c:930:13: warning: suggest parentheses around assignment used as truth value
EFflat.c:1152:12: warning: suggest parentheses around assignment used as truth value
EFflat.c:1157:13: warning: suggest parentheses around assignment used as truth value
EFhier.c:84:12: warning: suggest parentheses around assignment used as truth value
EFhier.c:261:12: warning: suggest parentheses around assignment used as truth value
EFhier.c:489:12: warning: suggest parentheses around assignment used as truth value
EFhier.c:682:12: warning: suggest parentheses around assignment used as truth value
EFname.c:325:12: warning: suggest parentheses around assignment used as truth value
EFname.c:584:13: warning: suggest parentheses around assignment used as truth value
EFname.c:632:16: warning: suggest parentheses around assignment used as truth value
EFname.c:765:16: warning: suggest parentheses around assignment used as truth value
EFname.c:977:12: warning: suggest parentheses around assignment used as truth value
EFsym.c:113:13: warning: suggest parentheses around assignment used as truth value
EFsym.c:164:9: warning: suggest parentheses around assignment used as truth value
EFvisit.c:322:12: warning: suggest parentheses around assignment used as truth value
EFvisit.c:627:12: warning: suggest parentheses around assignment used as truth value
EFvisit.c:881:16: warning: suggest parentheses around assignment used as truth value
EFvisit.c:917:12: warning: suggest parentheses around assignment used as truth value
grTk1.c:1325:9: warning: suggest parentheses around assignment used as truth value
grTk1.c:1342:9: warning: suggest parentheses around assignment used as truth value
grTk1.c:1757:9: warning: suggest parentheses around assignment used as truth value
grTk1.c:1766:9: warning: suggest parentheses around assignment used as truth value
grTk5.c:177:12: warning: suggest parentheses around assignment used as truth value
grTOGL1.c:1095:9: warning: suggest parentheses around assignment used as truth value
grTOGL1.c:1111:9: warning: suggest parentheses around assignment used as truth value
grTOGL1.c:1542:13: warning: suggest parentheses around assignment used as truth value
grTOGL1.c:1551:13: warning: suggest parentheses around assignment used as truth value
grTOGL5.c:201:12: warning: suggest parentheses around assignment used as truth value
grTCairo1.c:1093:13: warning: suggest parentheses around assignment used as truth value
grTCairo1.c:1109:13: warning: suggest parentheses around assignment used as truth value
grTCairo1.c:1493:21: warning: suggest parentheses around assignment used as truth value
grTCairo1.c:1502:21: warning: suggest parentheses around assignment used as truth value
grTCairo5.c:202:16: warning: suggest parentheses around assignment used as truth value
GCC14 -Wall cleanup series [-Wparentheses]
Fix code scanning alert no. 50: Multiplication result converted to larger type (#51)
Co-authored-by: Copilot Autofix powered by AI <62310815+github-advanced-security[bot]@users.noreply.github.com>
This commit makes the code (mostly) C99-compatible, enabling to compile
it without the -Wno-error=implicit-function-declaration flag. This
way, Magic becomes usable on arm64 architectures, specifically on Apple
computers with M1/M2 SoC.
substrate (bulk terminal) and global substrate. Otherwise, the
routine in ext2hier.c that finds the substrate node will find the
first device bulk connection, not the default substrate.
implements a method for handling ports in a subcircuit that have different
port names and indexes but are shorted together. "none" is the default
and backwards-compatible behavior that merges ports together, which will
often cause one of the ports to be optimized out of the netlist. "resistor"
will separate the port names with a 0-ohm ideal resistor. "voltage" will
separate the port names with a 0-volt voltage source. This should work
well for simulation and potentially for LVS, although its impact on LVS
has not been fully investigated.
not restored until after all cells have been processed through
extraction. Otherwise, top-down connections can end up with
different generated names for the same node, resulting in a
disconnect in the netlist.
extflat code; failure to provide a forward external reference
to EFHNBest() resulted in a failure to correctly evaluate a
boolean expression. That resulted in a failure to merge
hierarchical nodes during ext2spice, resulting in an incorrect
netlist with single nodes broken up into pieces.
change from passing the HierName to passing the HierContext (of which
HierName is a part) so that more information from HierContext (such
as the cell use being visited) can be passed to the callback
procedure (largely for diagnostic purposes).
with ext2spice without the hierarchy option. More work needed to
produce correct hierarchical output and to support extraction
devices other than the old "fet" record.
added a long time ago, since capacitors use a different method for
calculating width and length than either transistors or resistors,
so subcircuits need a special class designator or else the extraction
may calculate the wrong dimensions for device width by totalling the
perimeter between the device and terminal types, as it would for a
MOSFET.
R. Timothy Edwards
Darryl L. Miles
Alessandro De Laurenzis