mirror of https://github.com/KLayout/klayout.git
Updated 2019 01 07 (markdown)
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@ -118,11 +118,14 @@ Four-terminal devices with a bulk connection require the concept of global nets.
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global net represents the bulk (p-body) of the wafer. n-type transistors will have their bulk terminal
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connected to this virtual net. Such a net is represented by a global net. Global nets are inherited by
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parent circuits automatically. Global nets can be included in a connectivity specification with
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"connect_global". A MOS4 device extractor emits bulk terminal shapes as copies of the gate shape to
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a specified layer. When connecting this layer to the global "BULK" net, the B terminal of the
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"connect_global".
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A MOS4 device extractor emits bulk terminal shapes as copies of the gate shape to
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a layer as "W" input (well). When connecting this layer to the global "BULK" net, the "B" (bulk) terminal of the
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MOS4 devices will be connected to this global net.
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Here is code for such an extraction. It also recognizes tie-down diodes for substrate and well connections:
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Here is code for such an extraction. It also recognizes tie-down diodes for substrate and well connections. The p-tie-down diode will also connect to the "BULK" global net. The n diode will connect to the n-well area. n-well is
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included in the net extraction like a conductive layer.
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```ruby
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ly = RBA::Layout::new
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