mirror of https://github.com/KLayout/klayout.git
Created 2019 01 07 (markdown)
Matthias Köfferlein
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# 2019-01-07
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The latest version (dvb branch) is fairly stable and has been tested on a medium-size SoC thoroughly. Here are some numbers: Extraction of all nets takes ~1hr/7GB memory. With the net tracer, the extraction of the VSS net alone was taking 5hrs and 10GB of memory. The VSS net alone has about 30M shapes. After taking the shapes of all nets and outputting them to an OASIS file, the original layout was reproduced (with the exception of a few text marker shapes). This means that all nets are captured and no shape is lost. The VSS net from this extracted netlist is XOR-identical to the one delived by the net tracer.
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This was a pure backend extraction without devices.
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The script used for this extraction was similar to this one:
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```ruby
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top_cell = nil
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prefix = "xout"
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ly = RBA::Layout::new
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ly.read("layout.oas")
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tc = ly.top_cell
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l2n = RBA::LayoutToNetlist::new(RBA::RecursiveShapeIterator::new(ly, tc, []))
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# only plain connectivity
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puts "Making layers ..."
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rpoly = l2n.make_polygon_layer( ly.layer(1, 0 ) ) # GDS #1 -> poly
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rcont = l2n.make_polygon_layer( ly.layer(2, 0 ) ) # GDS #2 -> contact (poly or diff)
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rmetal1 = l2n.make_polygon_layer( ly.layer(3, 0 ) ) # GDS #3 -> metal 1
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rmetal1_lbl = l2n.make_text_layer( ly.layer(103,0 ) ) # GDS #103 -> metal 1 labels
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rvia1 = l2n.make_polygon_layer( ly.layer(4, 0 ) ) # GDS #4 -> via 1
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rmetal2 = l2n.make_polygon_layer( ly.layer(5, 0 ) ) # GDS #5 -> metal 2
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rmetal2_lbl = l2n.make_text_layer( ly.layer(105,0 ) ) # GDS #105 -> metal 2 labels
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rvia2 = l2n.make_polygon_layer( ly.layer(6, 0 ) ) # GDS #6 -> via 2
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rmetal3 = l2n.make_polygon_layer( ly.layer(7, 0 ) ) # GDS #7 -> metal 3
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rmetal3_lbl = l2n.make_text_layer( ly.layer(107,0 ) ) # GDS #107 -> metal 3 labels
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rvia3 = l2n.make_polygon_layer( ly.layer(8, 0 ) ) # GDS #8 -> via 3
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rmetal4 = l2n.make_polygon_layer( ly.layer(9, 0 ) ) # GDS #9 -> metal 4
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rmetal4_lbl = l2n.make_text_layer( ly.layer(109,0 ) ) # GDS #109 -> metal 4 labels
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rvia4 = l2n.make_polygon_layer( ly.layer(10, 0 ) ) # GDS #10 -> via 4
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rmetal5 = l2n.make_polygon_layer( ly.layer(11, 0 ) ) # GDS #11 -> metal 5
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rmetal5_lbl = l2n.make_text_layer( ly.layer(111,0 ) ) # GDS #111 -> metal 5 labels
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puts "Connecting ..."
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# Intra-layer
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l2n.connect(rpoly)
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l2n.connect(rcont)
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l2n.connect(rmetal1)
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l2n.connect(rvia1)
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l2n.connect(rmetal2)
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l2n.connect(rvia2)
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l2n.connect(rmetal3)
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l2n.connect(rvia3)
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l2n.connect(rmetal4)
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l2n.connect(rvia4)
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l2n.connect(rmetal5)
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# Inter-layer
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l2n.connect(rpoly, rcont)
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l2n.connect(rcont, rmetal1)
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l2n.connect(rmetal1, rvia1)
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l2n.connect(rvia1, rmetal2)
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l2n.connect(rmetal2, rvia2)
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l2n.connect(rvia2, rmetal3)
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l2n.connect(rmetal3, rvia3)
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l2n.connect(rvia3, rmetal4)
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l2n.connect(rmetal4, rvia4)
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l2n.connect(rvia4, rmetal5)
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l2n.connect(rmetal1, rmetal1_lbl) # attaches labels
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l2n.connect(rmetal2, rmetal2_lbl) # attaches labels
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l2n.connect(rmetal3, rmetal3_lbl) # attaches labels
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l2n.connect(rmetal4, rmetal4_lbl) # attaches labels
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l2n.connect(rmetal5, rmetal5_lbl) # attaches labels
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puts "Running netlist extraction ..."
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# Perform netlist extraction
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l2n.extract_netlist
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out = {
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1 => rpoly,
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2 => rcont,
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3 => rmetal1,
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103 => rmetal1_lbl,
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4 => rvia1,
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5 => rmetal2,
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105 => rmetal2_lbl,
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6 => rvia2,
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7 => rmetal3,
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107 => rmetal3_lbl,
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8 => rvia3,
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9 => rmetal4,
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109 => rmetal4_lbl,
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10 => rvia4,
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11 => rmetal5,
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111 => rmetal5_lbl
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}
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# write an annotated layout - all nets are put into
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# cells called "NET_" + net name. The nets are output
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# hierarchically where the circuits are put into cells
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# called "CIRCUIT_" + circuit name
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ly2 = RBA::Layout::new
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top2 = ly2.create_cell(net.expanded_name)
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lmap = {}
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out.each do |ln,r|
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lmap[ly2.layer(ln, 0)] = r
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end
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l2n.build_all_nets(l2n.cell_mapping_into(ly2, top2), ly2, lmap, "NET_", "CIRCUIT_")
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ly2.write("#{prefix}_all.oas.gz")
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ly2._destroy
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```
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## Support for extracting four-terminal MOS devices and global nets
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Four-terminal devices with a bulk connection require the concept of global nets. A specific
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global net represents the bulk (p-body) of the wafer. n-type transistors will have their bulk terminal
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connected to this virtual net. Such a net is represented by a global net. Global nets are inherited by
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parent circuits automatically. Global nets can be included in a connectivity specification with
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"connect_global". A MOS4 device extractor emits bulk terminal shapes as copies of the gate shape to
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a specified layer. When connecting this layer to the global "BULK" net, the B terminal of the
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MOS4 devices will be connected to this global net.
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Here is code for such an extraction. It also recognizes tie-down diodes for substrate and well connections:
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```ruby
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ly = RBA::Layout::new
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ly.read(File.join($ut_testsrc, "testdata", "algo", "device_extract_l3.gds"))
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l2n = RBA::LayoutToNetlist::new(RBA::RecursiveShapeIterator::new(ly, ly.top_cell, []))
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rbulk = l2n.make_polygon_layer( ly.layer )
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rnwell = l2n.make_polygon_layer( ly.layer(1, 0) )
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ractive = l2n.make_polygon_layer( ly.layer(2, 0) )
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rpoly = l2n.make_polygon_layer( ly.layer(3, 0) )
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rpoly_lbl = l2n.make_text_layer( ly.layer(3, 1) )
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rdiff_cont = l2n.make_polygon_layer( ly.layer(4, 0) )
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rpoly_cont = l2n.make_polygon_layer( ly.layer(5, 0) )
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rmetal1 = l2n.make_polygon_layer( ly.layer(6, 0) )
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rmetal1_lbl = l2n.make_text_layer( ly.layer(6, 1) )
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rvia1 = l2n.make_polygon_layer( ly.layer(7, 0) )
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rmetal2 = l2n.make_polygon_layer( ly.layer(8, 0) )
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rmetal2_lbl = l2n.make_text_layer( ly.layer(8, 1) )
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rpplus = l2n.make_polygon_layer( ly.layer(10, 0) )
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rnplus = l2n.make_polygon_layer( ly.layer(11, 0) )
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ractive_in_nwell = ractive & rnwell
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rpactive = ractive_in_nwell & rpplus
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rntie = ractive_in_nwell & rnplus
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rpgate = rpactive & rpoly
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rpsd = rpactive - rpgate
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ractive_outside_nwell = ractive - rnwell
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rnactive = ractive_outside_nwell & rnplus
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rptie = ractive_outside_nwell & rpplus
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rngate = rnactive & rpoly
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rnsd = rnactive - rngate
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# PMOS transistor device extraction
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pmos_ex = RBA::DeviceExtractorMOS4Transistor::new("PMOS")
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l2n.extract_devices(pmos_ex, { "SD" => rpsd, "G" => rpgate, "P" => rpoly, "W" => rnwell })
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# NMOS transistor device extraction
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nmos_ex = RBA::DeviceExtractorMOS4Transistor::new("NMOS")
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l2n.extract_devices(nmos_ex, { "SD" => rnsd, "G" => rngate, "P" => rpoly, "W" => rbulk })
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# Define connectivity for netlist extraction
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# Intra-layer
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l2n.connect(rpsd)
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l2n.connect(rnsd)
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l2n.connect(rnwell)
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l2n.connect(rpoly)
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l2n.connect(rdiff_cont)
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l2n.connect(rpoly_cont)
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l2n.connect(rmetal1)
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l2n.connect(rvia1)
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l2n.connect(rmetal2)
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l2n.connect(rptie)
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l2n.connect(rntie)
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# Inter-layer
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l2n.connect(rpsd, rdiff_cont)
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l2n.connect(rnsd, rdiff_cont)
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l2n.connect(rpoly, rpoly_cont)
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l2n.connect(rpoly_cont, rmetal1)
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l2n.connect(rdiff_cont, rmetal1)
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l2n.connect(rdiff_cont, rntie)
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l2n.connect(rdiff_cont, rptie)
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l2n.connect(rnwell, rntie)
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l2n.connect(rmetal1, rvia1)
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l2n.connect(rvia1, rmetal2)
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l2n.connect(rpoly, rpoly_lbl) # attaches labels
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l2n.connect(rmetal1, rmetal1_lbl) # attaches labels
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l2n.connect(rmetal2, rmetal2_lbl) # attaches labels
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# Global connections
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l2n.connect_global(rptie, "BULK")
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l2n.connect_global(rbulk, "BULK")
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# Perform netlist extraction
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l2n.extract_netlist
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puts l2n.netlist.to_s
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```
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