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klayout/testdata/lvs
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Matthias Koefferlein cef96902ad Boundary for circuits, reverted automatic generation of global pins 
- global pins have been generated for device cells too and lead
  to implicit pins which may not be desired. The original problem
  was how to make abstract circuits comparable. This has to be
  solved differently.
- Circuit boundaries are good for displaying the boxes for
  abstract circuits
 		2019-07-09 19:55:48 +02:00
..
inv.cir Added reference circuit 2019-07-02 00:30:50 +02:00
inv.lvs WIP: added more test data, doc links 2019-07-02 02:03:58 +02:00
inv.lvsdb Boundary for circuits, reverted automatic generation of global pins 2019-07-09 19:55:48 +02:00
inv.oas Added inverter test layout 2019-07-02 00:27:05 +02:00
inv2.cir WIP: added more test data, doc links 2019-07-02 02:03:58 +02:00
inv2.lvs WIP: added more test data, doc links 2019-07-02 02:03:58 +02:00
inv2.lvsdb Boundary for circuits, reverted automatic generation of global pins 2019-07-09 19:55:48 +02:00
inv2.oas WIP: added more test data, doc links 2019-07-02 02:03:58 +02:00
inv2_layout.cir WIP: one more test for LVS 2019-07-06 09:08:32 +02:00
inv_layout.cir WIP: refactoring, added first tests for LVS 2019-07-06 08:52:40 +02:00
ringo.cir Providing LVS tests. 2019-07-07 21:33:28 +02:00
ringo.gds Providing LVS tests. 2019-07-07 21:33:28 +02:00
ringo_for_blackboxing.cir WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
ringo_for_blackboxing.gds WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
ringo_for_simplification.cir WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
ringo_for_simplification.gds WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
ringo_implicit_connections.gds Providing LVS tests. 2019-07-07 21:33:28 +02:00
ringo_pin_swapping.cir WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
ringo_renamed.gds WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
ringo_simple.cir Providing LVS tests. 2019-07-07 21:33:28 +02:00
ringo_simple.lvs Providing LVS tests. 2019-07-07 21:33:28 +02:00
ringo_simple.lvsdb Boundary for circuits, reverted automatic generation of global pins 2019-07-09 19:55:48 +02:00
ringo_simple_blackboxing.cir WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
ringo_simple_blackboxing.lvs WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
ringo_simple_blackboxing.lvsdb WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
ringo_simple_implicit_connections.cir Providing LVS tests. 2019-07-07 21:33:28 +02:00
ringo_simple_implicit_connections.lvs Providing LVS tests. 2019-07-07 21:33:28 +02:00
ringo_simple_implicit_connections.lvsdb Boundary for circuits, reverted automatic generation of global pins 2019-07-09 19:55:48 +02:00
ringo_simple_io.cir Providing LVS tests. 2019-07-07 21:33:28 +02:00
ringo_simple_io.lvs Providing LVS tests. 2019-07-07 21:33:28 +02:00
ringo_simple_io.lvsdb Boundary for circuits, reverted automatic generation of global pins 2019-07-09 19:55:48 +02:00
ringo_simple_io2.cir Providing LVS tests. 2019-07-07 21:33:28 +02:00
ringo_simple_io2.l2n Boundary for circuits, reverted automatic generation of global pins 2019-07-09 19:55:48 +02:00
ringo_simple_io2.lvs Providing LVS tests. 2019-07-07 21:33:28 +02:00
ringo_simple_io2.lvsdb Boundary for circuits, reverted automatic generation of global pins 2019-07-09 19:55:48 +02:00
ringo_simple_net_and_circuit_equivalence.cir WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
ringo_simple_net_and_circuit_equivalence.lvs WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
ringo_simple_net_and_circuit_equivalence.lvsdb Boundary for circuits, reverted automatic generation of global pins 2019-07-09 19:55:48 +02:00
ringo_simple_pin_swapping.cir WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
ringo_simple_pin_swapping.lvs WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
ringo_simple_pin_swapping.lvsdb Boundary for circuits, reverted automatic generation of global pins 2019-07-09 19:55:48 +02:00
ringo_simple_same_device_classes.cir WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
ringo_simple_same_device_classes.lvs WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
ringo_simple_same_device_classes.lvsdb Boundary for circuits, reverted automatic generation of global pins 2019-07-09 19:55:48 +02:00
ringo_simple_simplification.cir WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
ringo_simple_simplification.lvs WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
ringo_simple_simplification.lvsdb Boundary for circuits, reverted automatic generation of global pins 2019-07-09 19:55:48 +02:00
vexriscv.cir.gz WIP: added full LVS test. 2019-07-08 21:43:06 +02:00
vexriscv.lvs WIP: reverted modifications on SPICE reader. 2019-07-08 21:51:59 +02:00
vexriscv.oas.gz WIP: added full LVS test. 2019-07-08 21:43:06 +02:00
vexriscv_schematic.cir.gz WIP: added full LVS test. 2019-07-08 21:43:06 +02:00