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klayout
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16 Commits

Author SHA1 Message Date
Matthias Koefferlein ebcf242a9e Merge branch 'more-spice' into issue-1304 2023-02-27 00:21:20 +01:00
Matthias Koefferlein 69d975c736 Update to test data 2023-02-27 00:19:14 +01:00
Matthias Koefferlein d20e4b2128 Bug fixes, adjusted test data 2023-02-22 15:54:28 +01:00
Matthias Koefferlein 90df9451b6 WIP: reworked log enabling in LVS, added 'no_lvs_hints' feature, updated tests 2022-08-13 18:30:02 +02:00
Matthias Köfferlein 4a06bc1bb5
Another change related to issue-1011 (aligning flat and deep mode text representation for LVS) (#1037) 2022-03-16 23:33:08 +01:00
Matthias Koefferlein 19b28982e7 WIP: updated test data (bugfix: bulk does not have layer properties), Fixed Region::count and Region::hier_count (was counting non-polygons too) 2021-05-25 23:08:38 +02:00
Matthias Koefferlein 03dacbd2f5 Updated testdata 2020-06-26 17:46:39 +02:00
Matthias Koefferlein 782f6fe601 BUGFIX: the L2N and LVSDB writer was writing too much 
Sometimes, shapes from child cells were propagated into
parent cells in the L2N and LVSDB output.

Because of this fix, many testdata files have to be updated.
 2019-12-15 01:29:56 +01:00
Matthias Koefferlein 96e591cba9 WIP: further updates of test data. 2019-12-15 00:23:05 +01:00
Matthias Koefferlein 64bb01d80d Dropped attempt to remove dummy nodes from spice reader netlist as this wasn't effective anyway. 2019-11-24 00:23:19 +01:00
Matthias Koefferlein ed00503d41 Fixed Spice reader: must not use Netlist::purge_nets to remove dummy nets. Updated golden test data. 2019-11-23 23:36:52 +01:00
Matthias Koefferlein e25d4784ea Updated tests. 2019-10-26 01:48:50 +02:00
Matthias Koefferlein bdf5e3c124 WIP: fake pin debug issue with LVS 
Fake pins: pins that happen because something connects to a cell at an
unexpected position. Such a pin is difficult to find. The solution is
to keep those nets and nur purge them so these nets can be identified
in the layout.

Here: is_floating? will be true only if there are no pins. Hence
nets with pins are not removed. is_passive is introduced for nets -
passive nets are such that don't have elements, but a pin.
Circuits are purged if they only have passive nets.
 2019-09-30 21:58:13 +02:00
Matthias Koefferlein 60ed0cdc89 Updated test golden data (mainly: nets are not purged when there is a subcircuit pin on it) 2019-08-29 23:26:03 +02:00
Matthias Koefferlein 71f646c24f WIP: updated test data for latest updates, don't sort LVSDB on reading for consistency 2019-07-27 21:42:51 +02:00
Matthias Köfferlein 4e1736a181 Updated golden data of two tests for Windows. 2019-07-16 01:27:08 +02:00