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29 Commits

Author SHA1 Message Date
Matthias Koefferlein 9613ad72c8 WIP: netlist compare - using it for more tests 
Issue solved: some circuit pins may not have a net - these
need to be ignored.

Requirement: all pins with a net must be mapped.

Detached pins are not present in the mapping table.
A dummy mapping table was introduced to allow dropping
of pins in the second circuit too.

Output of compare should not depend on memory location
anymore and pin mismatch reporting should include all
pins.
 2019-03-31 23:59:43 +02:00
Matthias Koefferlein 06e326dfd9 WIP: netlist compare - some more tests by netlist compare. Needs fixing. 2019-03-31 19:00:42 +02:00
Matthias Koefferlein 2d4f23abd1 Updated tests. 2019-03-19 00:08:47 +01:00
Matthias Koefferlein d7eb9162ce WIP: unified to_string/to_parsable_string of db::Netlist, step 1 2019-03-18 19:28:20 +01:00
Matthias Koefferlein 6932977273 A few bug fixes and test updates 
- edge pairs are normalized before turning them into polygons.
  This makes flat and deep implementation more consistent.
- deep region and flat regions were not cooperating in geo
  checks
- unnamed layers are not registered in make_layer - this
  does not make sense and will just hold a fake ref
- tests now use GDS to represent texts after transformation
  (with orientation, OASIS can't do this)
- texts are more consistently handled in the tests
- test debug output is not written in the same format
  than golden data unless special normalization is
  requested.
- a non-orientable polygon was converted to orientable in
  a text because this can be represented in GDS consistently
- DRC testsuite uses "polygons" instead of "input" to achieve
  identical behavior for deep and flat mode with respect to
  texts
- dbRegionTests are updated because texts are not allowed
  for non-original layers too
 2019-03-09 19:40:38 +01:00
Matthias Koefferlein 261fb027fd GSI binding of antenna check function + tests. 2019-03-02 00:38:51 +01:00
Matthias Koefferlein 8d3b94201e Antenna check: tests added, 'catchall' diode protection 2019-03-01 23:07:28 +01:00
Matthias Koefferlein 9f4f2d58d7 First version of antenna check. 2019-02-28 23:56:49 +01:00
Matthias Koefferlein 4035c804b7 WIP: fixed bugs, added tests. 2019-02-28 22:23:20 +01:00
Matthias Koefferlein 36a3540e16 Allow empty regions for device extractor. 2019-02-25 23:51:21 +01:00
Matthias Koefferlein 21ea37f747 Updated test golden data. 2019-02-25 22:52:37 +01:00
Matthias Koefferlein d4ed21f42a Just new tests 2019-02-25 22:34:06 +01:00
Matthias Koefferlein c90f7e4af9 Introduced perimeter parameters for MOS3/MOS4 2019-02-02 01:29:28 +01:00
Matthias Koefferlein f83e1dae43 Refactoring, some bugfixes, GSI bindings for L2N methods. 2019-01-20 23:12:27 +01:00
Matthias Koefferlein 5962d66940 WIP: major enhancements with respect to device handling 
The device handling in the netlist extractor was now
entirely moved to device cells. New options are introduced
for exporting these cells. Tests have been updated.
 2019-01-15 21:33:41 +01:00
Matthias Koefferlein 9fa5618034 Added test for device combination. 2019-01-08 23:49:12 +01:00
Matthias Koefferlein d4d7ea8022 Updated copyright. 2019-01-08 01:09:25 +01:00
Matthias Koefferlein 315bcdd016 WIP: bugfixed netlist extractor with global nets. 2019-01-07 23:33:57 +01:00
Matthias Koefferlein c80e335cd6 WIP: global nets integration in cluster builder. 2019-01-07 02:08:59 +01:00
Matthias Koefferlein a4f0fd665e Provided a solution for connectivity through global nets. 2019-01-06 17:50:51 +01:00
Matthias Koefferlein eb435d5d85 WIP: refactoring - separated pins of net into outgoing and subcircuit. 2019-01-06 12:53:22 +01:00
Matthias Koefferlein ec3a3b0f8c WIP: added ability to export nets to layouts. 2019-01-06 01:32:20 +01:00
Matthias Koefferlein bc4f9efa5d One more test for probing with a slightly more complex hierarchy. 2019-01-05 23:21:37 +01:00
Matthias Koefferlein ad6d9b5715 WIP: provide a less memory intensive way to deliver shapes from nets. 2019-01-04 17:41:09 +01:00
Matthias Koefferlein 76330bea3a Save some memory on net shape retrieval. 2019-01-02 23:23:04 +01:00
Matthias Koefferlein 9c607d7663 Added a first version of the layout to netlist extraction feature 
The main entry point is RBA::LayoutToNetlist which is the
GSI binding for the layout to netlist extractor. For a first
impression about the abilities of this extractor see the
Ruby tests in testdata/ruby/dbLayoutToNetlist.rb.

The framework itself consists of many classes, specifically

- RBA::Netlist for the netlist representation
- RBA::DeviceClass and superclasses (e.g. RBA::DeviceClassResistor and
  RBA::DeviceClassMOS3Transistor) for the description of devices.
- RBA::DeviceExtractor and superclasses (i.e. RBA::DeviceExtractorMOS3Transistor or
  the generic RBA::GenericDeviceExtractor) for the implementation of the
  device extraction.
- RBA::Connectivity for the description of inter- and intra-layer connections.
 2018-12-30 22:43:56 +01:00
Matthias Koefferlein f989a85642 WIP: introduced Circuit::is_external_net 2018-12-30 18:44:30 +01:00
Matthias Koefferlein 72a140957d WIP: added test for recursive net shape retrieval 2018-12-30 18:22:45 +01:00
Matthias Koefferlein 16a2b1982d WIP: added one more level of abstraction to layout-to-netlist extraction (db::LayoutToNetlist) for easier use. 2018-12-30 17:53:46 +01:00